| Age | Commit message (Collapse) | Author | 
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|  | 1. DRM_NOUVEAU_GPUOBJ_FREE
	Used to free GPU objects.  The obvious usage case is for Gr objects,
	but notifiers can also be destroyed in the same way.
	GPU objects gain a destructor method and private data fields with
	this change, so other specialised cases (like notifiers) can be
	implemented on top of gpuobjs.
2. DRM_NOUVEAU_CHANNEL_FREE
3. DRM_NOUVEAU_CARD_INIT
	Ideally we'd do init during module load, but this isn't currently
	possible.  Doing init during firstopen() is bad as X has a love of
	opening/closing the DRM many times during startup.  Once the
	modesetting-101 branch is merged this can go away.
	IRQs are enabled in nouveau_card_init() now, rather than having the
	X server call drmCtlInstHandler().  We'll need this for when we give
	the kernel module its own channel.
4. DRM_NOUVEAU_GETPARAM
	Add CHIPSET_ID value, which will return the chipset id derived
	from NV_PMC_BOOT_0.
4. Use list_* in a few places, rather than home-brewed stuff. | 
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|  | This extra increase was causing fence leaks on my system, due to create/user add already increasing it twice no need for a 3rd go. | 
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|  | This patch removes some obviously dead code spotted by the Coverity
checker.
Signed-off-by: Adrian Bunk <bunk@stusta.de> | 
|  | Debug print fix in drm_release().
Forgotten local variable init in drm_setversion().
Unnecessary put_user() in drm_addmap_ioctl().
ioctl->cmd check broken in drm_ioctl(); workaround. | 
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|  | The data is now in kernel space, copied in/out as appropriate according to the
This results in DRM_COPY_{TO,FROM}_USER going away, and error paths to deal
with those failures.  This also means that XFree86 4.2.0 support for i810 DRM
is lost. | 
|  | As a fallout, replace filp storage with file_priv storage for "unique
identifier of a client" all over the DRM.  There is a 1:1 mapping, so this
should be a noop.  This could be a minor performance improvement, as everything
on Linux dereferenced filp to get file_priv anyway, while only the mmap ioctls
went the other direction. | 
|  | This was used to make all ioctl handlers return -errno on linux and errno on
*BSD.  Instead, just return -errno in shared code, and flip sign on return from
shared code to *BSD code. | 
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|  | With this, all modules build again. | 
|  | Fix by Simon Farnsworth, Bugzilla Bug #11542
http://bugs.freedesktop.org/show_bug.cgi?id=11542 | 
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|  | This might break something, stdint.h inclusion in drm.h maybe required
but I'm not sure yet what platforms have it what ones don't. | 
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|  | Actually a NV04-NV50 ttm backend for both PCI and PCIEGART, but PCIGART
support for G8X using the current mm has been hacked on top of it. | 
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|  | Conflicts:
	libdrm/xf86drm.c
	linux-core/drm_bo.c
	linux-core/drm_fence.c | 
|  | ioctl wrapper | 
|  | Should be OK on G84 for a single channel, multiple channels *almost* work.
Untested on G80. | 
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|  | Dave Airlie pointed out on IRC that idr_replace lets us know if the ID hasn't
been allocated, so we don't need a special pointer value for allocated IDs that
don't have valid information yet. | 
|  | There's a difference between a drawable ID not having valid drawable
information and not being allocated at all. Not making the distinction would
break i915 DRM swap scheduling with older X servers that don't push drawable
cliprect information to the DRM. | 
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|  | Buffer object dereference cleanup.
Add a struct drm_device member to fence objects:
This can simplify code, particularly in drivers. | 
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|  | For various reasons, this ioctl was a bad idea.
At channel creation we now automatically create DMA objects covering
available VRAM and GART memory, where the client used to do this themselves.
However, there is still a need to be able to create DMA objects pointing at
specific areas of memory (ie. notifiers).  Each channel is now allocated a
small amount of memory from which a client can suballocate things (such as
notifiers), and have a DMA object created which covers the suballocated area.
The NOTIFIER_ALLOC ioctl exposes this functionality. | 
|  | Earlier NV1X chips use the NV04 code, see previous commits about NV10 RAMFC
entry size. |