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xgi-0-0-2
Conflicts:
linux-core/drmP.h
linux-core/drm_scatter.c
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Actually a NV04-NV50 ttm backend for both PCI and PCIEGART, but PCIGART
support for G8X using the current mm has been hacked on top of it.
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Should be OK on G84 for a single channel, multiple channels *almost* work.
Untested on G80.
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For various reasons, this ioctl was a bad idea.
At channel creation we now automatically create DMA objects covering
available VRAM and GART memory, where the client used to do this themselves.
However, there is still a need to be able to create DMA objects pointing at
specific areas of memory (ie. notifiers). Each channel is now allocated a
small amount of memory from which a client can suballocate things (such as
notifiers), and have a DMA object created which covers the suballocated area.
The NOTIFIER_ALLOC ioctl exposes this functionality.
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Earlier NV1X chips use the NV04 code, see previous commits about NV10 RAMFC
entry size.
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The PGRAPH init for the various cards will need cleaning up at some point,
a lot of the values written there are per-context state left over from the
all the hardcoding done in the ddx.
It's possible some cards get broken by this commit, let me know.
Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
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Buffer object driver for via.
Some changes to buffer object driver callbacks.
Improve fence flushing.
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Add a file for memory move helpers, drm_bo_move.c
Implement generic memory move.
Cached, no_move and unmapped memory temporarily broken.
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Untested...
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It is still not working, but now we could use some 3D commands
without needed to run nvidia blob before.
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* Pulled in some registers from nv10reg.h. Needed for context switching.
* Filled in nv30 graphics context (based on nv40_graph.c).
* Figure out nv30 context table, set up on context creation. Allows the cards automatic switching to work.
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Conflicts:
linux-core/Makefile.kernel
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Buffer object code.
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0x00 EXE fence. Signals when command stream interpreter has reached the point
where the fence was emitted.
0x01 FLUSH fence. Signals when command stream interpreter has reached the point
where the fence was emitted, and all previous drawing operations have been
completed and flushed.
Implements busy wait (for fastest response time / high CPU) and
lazy wait (User interrupt or timer driven).
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Add drm_fence.o to Makefile
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fence objects and buffer objects:
Refcounting,
Inter-process sharing,
Synchronization
Destruction.
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me)
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suspend, and the DDX driver re-inits the board successfully anyway.
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with BSD fix from jkim and the r300_reg.h license from Nicolai Haehnle.
Big thanks to everyone involved!
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This is Egberts code, ported to Pauls framework by me..
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the code for it, rather than introducing something that isn't going to
work 100% of the time.
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radeonfb.
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There's two choices when fb is or isn't loaded as we treat ourselves as a
PCI driver in the latter case.
If we are a PCI driver, then register the suspend/resume functions
directly. If not, then we register as a sysdev and pick up the
suspend/resume actions and pump them down into a generic *power
function.
It'll be nice when this little mess is sorted out with regard to being a
real PCI driver ;-/
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New PCI command parser. Moved from via_dma.c to via_verifier.c so functions
with similar functionality are close to eachother.
Moved video related functions to via_video.c, which might be extended in
the future, as new video functionality is added.
New device-specific generic IRQ IOCTL, similar to the general VBLANK IOCTL,
but with support for multiple device IRQ sources and functionality.
Support for Unichrome Pro PM800/CN400 video DMA commands in verifier and
PCI parser.
Support for Unichrome Pro PM800/CN400 HQV IRQs in the new generic IRQ
IOCTL.
Bumped minor. New version 2.6.0.
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implementation errors). Direct hardware (MMIO, BCI) access is no longer
needed in the Mesa driver. Bumped version to 2.0.0. Corresponding
changes to the DDX and Mesa drivers are being committed.
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ring-buffer code somewhat to workaround hardware problems. Bumped via
minor version number.
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