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2008-05-27[BSD] Fix lock leaks in error paths in drm_bufs.c.Owain Ainsworth
2008-05-27[BSD] Remove superfluous recursive locking in drm_add_magic.Owain Ainsworth
2008-05-27[i915] Fix typo in (unused) START_ADDR definition.Jie Luo
2008-05-27[FreeBSD] Add vblank-rework support and get drivers building.Robert Noland
The i915 driver now works again.
2008-05-27[FreeBSD] Convert from drm_device_t to struct drm_device for consistency.Eric Anholt
2008-05-26[intel-gem] Must hold DRM lock while setting object domainKeith Packard
Object domain transfer can involve adding flush ops to the request queue, and so the DRM lock must be held to avoid having the X server smash pointers badly.
2008-05-26[i915] leave interrupts masked off when not in use.Keith Packard
The interrupt enable register cannot be used to temporarily disable interrupts, instead use the interrupt mask register. Note that this change means that a pile of buffers will be left stuck on the chip as the final interrupts will not be recognized to come and drain things.
2008-05-25[intel-gem] Add DRM_I915_GEM_BUSY ioctl to check for idle buffers.Keith Packard
This new ioctl returns whether re-using the buffer would force a wait.
2008-05-25[intel-gem] Compute npages instead of nbytes in flush_pwriteKeith Packard
i915_gem_flush_pwrite optimizes short writes to the buffer by clflushing only the modified pages, but it was miscomputing the number of pages.
2008-05-25[intel-gem] replace call to jiffies_to-msec with simple inlineKeith Packard
2008-05-22[intel-gem] Encourage multiple caches to hold read dataKeith Packard
When reading from multiple domains, allow each cache to continue to hold data until writes occur somewhere. This is done by first leaving the read_domains alone at bind time (presumably the CPU read cache contains valid data still) and then in set_domain, if no write_domain is specified, the new read domains are simply merged into the existing read domains. A huge comment was added above set_domain to explain how things are expected to work.
2008-05-22[gem] Use CPU domain for new or pageable objectsKeith Packard
Newly allocated objects need to be in the CPU domain as they've just been cleared by the CPU. Also, unmapping objects from the GTT needs to put them into the CPU domain, both to flush rendering as well as to ensure that any paging action gets flushed before we remap to the GTT.
2008-05-22[intel-gem] Force ring retire by emiting flush before user-interrupt.Keith Packard
Commands in the ring are parsed and started when the head pointer passes by them, but they are not necessarily finished until a MI_FLUSH happens. This patch inserts a flush after the execbuffer (the only place a flush wasn't already happening).
2008-05-22[intel] Add debug code to verify the cached ring tail pointer.Keith Packard
Recording the tail pointer in a local variable improves performance, but if someone messes up and fails to reload at the right time, the driver will write commands to the wrong part of the ring and scramble execution badly. This change (available by setting I915_RING_VALIDATE to 1) checks to make sure the cached tail pointer matches the hardware tail pointer at each ring buffer addition, calling BUG_ON when that's not true.
2008-05-22[intel-gem] invalidate ring locals for pin/unpin/set_domain/free functionsKeith Packard
Ring locals must be reloaded from hardware in case the X server ran.
2008-05-22[gem] Release GEM buffers from work task scheduled from IRQ.Eric Anholt
There are now 3 lists. Active is buffers currently in the ringbuffer. Flushing is not in the ringbuffer, but needs a flush before unbinding. Inactive is as before. This prevents object_free → unbind → wait_rendering → object_reference and a kernel oops about weird refcounting. This also avoids an synchronous extra flush and wait when freeing a buffer which had a write_domain set (such as a temporary rendered to and then from using the 2d engine). It will sit around on the flushing list until the appropriate flush gets emitted, or we need the GTT space for another operation.
2008-05-23r500: add two more register ranges for mesa driver to setupDave Airlie
2008-05-23drm: fix nouveau warningDave Airlie
2008-05-21[gem] Replace ring throttling hack with actual time measurement.Eric Anholt
2008-05-21[gem] Fix bad test for list_for_each completion.Eric Anholt
Since it's a circular list, the entry won't be NULL at termination.
2008-05-21[gem] Hold a reference on the object in i915_gem_wait_space.Eric Anholt
Otherwise, in the middle of the function called using it the last ref might disappear.
2008-05-21[intel-gem] invalidate ring locals for pin/unpin/set_domain/free functionsKeith Packard
Ring locals must be reloaded from hardware in case the X server ran.
2008-05-21rs690/r500: vblank support.Dave Airlie
The new display controller has the vblank interrupts in a different place. Add support for vbl interrupts for these chips
2008-05-20[gem] Use a separate sequence number field from classic/ttmEric Anholt
This lets us get some qualities we desire, such as using the full 32-bit range (except zero), avoiding DRM_WAIT_ON, and a 1:1 mapping of active sequence numbers to request structs, which will be used soon for throttling and interrupt-driven list cleanup.
2008-05-20[gem] Rename sequence numbers from "cookie" to "seqno"Eric Anholt
2008-05-20[gem] Clean up active/inactive list handling using helper functions.Eric Anholt
Additionally, a boolean active field is added to indicate which list an object is on, rather than smashing last_rendering_cookie to 0 to show inactive. This will help with flush-reduction later on, and makes the code clearer.
2008-05-17r500: add more register ranges for Mesa driverDave Airlie
2008-05-15[gem] Hold dev->struct_mutex to protect structure data.Eric Anholt
2008-05-15[gem] Rename the GTT LRU lists to active (executing) and inactive (idle).Eric Anholt
2008-05-15[gem] typo fix in comment.Eric Anholt
2008-05-14ati_pcigart: oops wrong way around not that it actually matteredDave Airlie
2008-05-14ati_pcigart: stop working in the evenings you mess up too oftenDave Airlie
2008-05-14Revert "ati_pcigart: fixup properly this version might even work"Dave Airlie
This reverts commit bc0836e12a9790f1cc83f8bc29bc05043c4bc840. tree has some kref hacks in it - oops
2008-05-14ati_pcigart: fixup properly this version might even workDave Airlie
2008-05-14ati_pcigart: fill out 40-bit gart table support properlyDave Airlie
Thanks to Alex for supplying this info.
2008-05-13RS4xx: separate out RS400 and RS480 IGP chipsAlex Deucher
RS400 (intel based IGP) and RS480 (AMD based IGP) have different MC and GART setups. Currently we only support RS480.
2008-05-12[GEM] Update testcases for new API.Eric Anholt
2008-05-12[GEM] Typo (and thinking) fixes in drm-gem.txt and doxygen.Eric Anholt
2008-05-12[intel] Minor kludge -- wait for the ring to be nearly empty before queuingKeith Packard
No need to fill the ring that much; wait for it to become nearly empty before adding the execbuffer request. A better fix will involve scheduling ring insertion in the irq handler.
2008-05-12[intel] When polling for ring space, sleep for a lot longer (10ms)Keith Packard
If the ring is full, the engine will surely be running for more than 10ms.
2008-05-12[gem] Set write domain to CPU when doing pwrite.Keith Packard
Leave the flush call in place, which can fix domains up if necessary.
2008-05-12[gem] Clarify use of explicit domain control. Remove Gen3 from I-cache usage.Keith Packard
2008-05-12RADEON: fix copy/pasto in last commitAlex Deucher
2008-05-12R3/4/5: init pipe setup in drmAlex Deucher
Similar (broken) code in mesa needs to be removed
2008-05-12RADEON: cleanup radeon_do_engine_reset()Alex Deucher
2008-05-12R300+: fixup pixcache flushAlex Deucher
2008-05-12RS4xx: fix MCIND index maskAlex Deucher
2008-05-12RADEON: write AGP_BASE_2 on chips that support itAlex Deucher
2008-05-12R300+: fixup PURGE/FLUSH macrosAlex Deucher
2008-05-12Radeon IGP: merge RS4xx/RS6xx gart setupAlex Deucher