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2014-01-10intel: Merge latest i915_drm.hBen Widawsky
This was not done as a straight copy because reset_stats IOCTL landed in libdrm before upstream kernel. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2014-01-10intel: Handle malloc fails in context createBen Widawsky
The previous code would just use the potentially unallocated variable, which is probably okay most of the time, but not very nice to the user of the library. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2014-01-10intel: squash unused variable 'bo_gem'Ben Widawsky
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2014-01-08Bump the version to 2.4.51Rob Clark
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-07freedreno: allow IB to different ringbufferRob Clark
Allow IB to different ringbuffer in addition to just different part of same ringbuffer. In particular, we need to add bo's to the parent (ie. one passed to flush) bo table, since the bo table applies to all the cmd buffers in submit ioctl. Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-07freedreno/kgsl: fix crash introduced w/ bo-cacheRob Clark
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-12-24radeon: fix sumo2 pci idAlex Deucher
0x9649 is sumo2, not sumo. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-12-24radeon: avoid possible divide by 0 in surface managerAlex Deucher
Some users report hitting a divide by 0 with the tile split in certain apps. Tile_split shouldn't ever be 0 unless the surface structure was not properly initialized. I think there may be some cases where mesa uses an improperly initialized surface struct, but I haven't had time to track it down. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=72425 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2013-12-13freedreno: add bo cacheRob Clark
Workloads which create many transient buffers cause significant CPU overhead in buffer allocation, zeroing, cache maint, and mmap setup. By caching and re-using existing buffers, the CPU overhead drops significantly. See: http://bloggingthemonkey.blogspot.com/2013/09/freedreno-update-moar-fps.html A simple time based policy is used for purging the cache. Once the kernel supports it, we could use madvise style API to handle memory pressure scenarios a bit better. Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-12-13intel/test_decode: Allow gen8 to be infered from the batch filenamesDamien Lespiau
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-12-13gitignore: Ignore various generated filesDamien Lespiau
- *.log/*.trs are generated by make check - TAGS are generated by make tags - build-aux, config.h.in~ by autoconf - *.sw? are temporary files create by vim - name_from_fd wasn't ignored yet for some reason v2: Ignore *~ as well (Daniel Vetter) Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-12-03Bump the version to 2.4.50Marek Olšák
2013-11-26 intel: Track known prime buffers for re-useKeith Packard
If the application sends us a file descriptor pointing at a prime buffer that we've already got, we have to re-use the same bo_gem structure or chaos will result. Track the set of all known prime objects and look to see if the kernel has returned one of those for a new file descriptor. Also checks for prime buffers in the flink case. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-26radeon: Update unaligned offset for 2D->1D tiling transition on SIMichel Dänzer
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71983 Tested-by: Arek Ruśniak <arek.rusi@gmail.com>
2013-11-23Bump the version for releaseMarek Olšák
2013-11-23radeon: handle P16 pipe configs for HawaiiMarek Olšák
2013-11-23radeon: don't overallocate stencil by 4 on SI and CIKMichel Dänzer
Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
2013-11-23radeon: implement 2D tiling for CIKMarek Olšák
Bug fixes and simplification by Marek. We have to use the tile index of 0 for non-MSAA depth-stencil after all. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-23radeon: fix mipmap level 0 and 1 alignment for SI and CIKMichel Dänzer
Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-20intel: Use memset instead of VG_CLEARIan Romanick
The ioctl expects that certain fields will be zeroed, so we should allow the helper function to actually work in non-Valgrind builds. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reported-by: Zhenyu Wang <zhenyuw@linux.intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-19libdrm/mode: Update the encoder and connector definesThomas Hellstrom
Update the defines to match the kernel drm_mode.h Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-15libdrm: bump to 2.4.48Ian Romanick
2013-11-15intel: Add support for GPU reset status query ioctlIan Romanick
I would have just used the drmIoctl interface directly in Mesa, but the ioctl needs some data from the drm_intel_context that is not exposed outside libdrm. This ioctl is in the drm-intel-next tree as b635991. v2: Update based on Mika's kernel work. v3: Fix compile failures from last-minute typos. Sigh. v4: Import the actual changes from the kernel i915_drm.h. Only comments on some fields of drm_i915_reset_stats differed. There are still some deltas between the kernel i915_drm.h and the one in libdrm, but those can be resolved in other patches. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v3] Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-13radeon: add hawaii pci idsAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-13radeon: add hawaii chip familyAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08Revert "intel: Add support for GPU reset status query ioctl"Dave Airlie
This reverts commit 6335e1d28c422050024bcf4100c4fb3a5bac2afb. No taxation without representation, in other words no userspace without kernel stuff being in a stable location, either drm-next but I'll accept drm-intel-next for intel specific stuff.
2013-11-07intel: Add support for GPU reset status query ioctlIan Romanick
I would have just used the drmIoctl interface directly in Mesa, but the ioctl needs some data from the drm_intel_context that is not exposed outside libdrm. v2: Update based on Mika's kernel work. v3: Fix compile failures from last-minute typos. Sigh. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-07intel/bdw: Update MI_BATCH_BUFFER_START for aub dumpsDamien Lespiau
The command now takes a 48bits address and is thus 1 dword longer. v2 (Ben): commit message: s/byte/dword (Eric) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-07intel/bdw/aub: Update AUB trace block writes for 48-bit addressing.Kenneth Graunke
Since our aub file dumping's GTT handling is totally fake, we always put everything in the low 4GB anyway and shouldn't ever need to set AddressHigh to anything other than 0. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> [ben: slight commit message change] Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-07intel/bdw: Add gen8 to the decode initDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-07intel/bdw: Handle gen8 bufmgr_initBen Widawsky
[bwidawsk: Added Damien's SOB] Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-07intel/bdw: Add broadwell chipset IDsBen Widawsky
v2: Rename s/<SECRET>/IRIS/ Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-07nouveau: prevent undefined behavior in nouveau_pushbuf_reloc with gcc-4.8Maarten Lankhorst
Reported-by: ronald645@gmail.com Bisected-by (gcc): Andreas Radke <a.radke@arcor.de> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71116 Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
2013-11-06Add DRM_MODE_PAGE_FLIP_ASYNC defineKeith Packard
This exposes the kernel API for performing asynchronous flips Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-10-29intel: Add MI_LOAD_REGISTER_MEM to intel_decode.c.Kenneth Graunke
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
2013-10-29intel: Add the Gen6+ version of MI_REPORT_PERF_COUNT to intel_decode.c.Kenneth Graunke
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
2013-10-11libdrm: bump to 2.4.47Ben Widawsky
2013-10-10intel: Set bo size from lseek if kernel supports itKristian Høgsberg
The various create and open functions set the buffer size, but drm_intel_bo_gem_create_from_prime() is an exception. In the 3.12 kernel we can now use lseek on the prime fd to determine the size of the bo. Use that and override the userprovided size. If the kernel doesn't support this, we get an error and fall back to the user provided size. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
2013-09-30drm: Introduce a drmSetClientCap() wrapperDamien Lespiau
That wraps around the new DRM_SET_CLIENT_CAP ioctl. v2: SET_CAP -> SET_CLIENT_CAP renaming Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-09-30drm: Sync the DRM_SET_CLIENT_CAP ioctl definitionDamien Lespiau
v2: SET_CAP -> SET_CLIENT_CAP renaming Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-09-30drm: Synchronize the stereo 3D mode flags from the kernel headersDamien Lespiau
v2: stereo layouts are now an enum (Daniel Vetter) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-09-29radeon: fix pitch alignment for non-power-of-two mipmaps on SIMarek Olšák
This fixes VM protection faults. I have a new piglit test which can iterate over all possible widths, heights, and depths (including NPOT) and tests mipmapping with various texture targets. After this is committed, I'll make a new release of libdrm and bump the libdrm version requirement in Mesa.
2013-09-24configure: add AC_LANG_SOURCE call within AC_COMPILE_IFELSEEmil Velikov
Documentation states that AC_*_IFELSE has to use AC_LANG_SOURCE or friends in order to generate the source code to compile. AC_LINK_IFELSE already handles this, thus convert AC_COMPILE_IFELSE to silence the final autoconf warnings. Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
2013-09-22libdrm: Make some drm headers compatible with gcc -std=c89 -pedanticDaniel Kurtz
The following minor changes were needed to these headers: * Convert // comments to /* */ * No , after final member of enum With these changes, these header files can be included by a program that is built with gcc options: -std=c89 -Werror -pedantic Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-09-18radeon: Fix tiling mode index for 1D tiled depth/stencil surfaces on CIKMichel Dänzer
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-11freedreno: add missing NOSYNC flagRob Clark
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-09-11modetest: allow setting a scaling factor when showing planeIlia Mirkin
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Rob Clark <robdclark@gmail.com>
2013-09-11modetest: add a -D option to specify a device to be usedIlia Mirkin
This is helpful for differentiating between multiple devices that use the same module. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Rob Clark <robdclark@gmail.com>
2013-09-06radeon: pad CS to 8 DWAlex Deucher
Aligns the IB to 8 DWs. The aligns the IB to the CP fetch size. r6xx also require at least 4 DW alignment to avoid a hw bug. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-06radeon: add berlin pci idsAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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