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2007-04-01nouveau : nv10 ctx switch fixMatthieu Castet
restoring NV10_PGRAPH_CTX_SWITCH1 now works
2007-04-01radeon: enable buffer managerDave Airlie
2007-04-01radeon: de-static irq function, fixup fence/bufferDave Airlie
2007-04-01copy over some files and reorg radeon to add ttm fencing not working yetDave Airlie
2007-04-01nouveau : set the correct PGRAPH_CTX_CONTROL registerMatthieu Castet
"5a072f32 (Stephane Marchesin 2007-02-03 04:57:06 +0100" broke nv10 ctx switch by setting wrong PGRAPH_CTX_CONTROL reg
2007-03-30Merge branch 'crestline-qa', adding support for the 965GM chipset.Eric Anholt
2007-03-30Merge branch 'origin'Eric Anholt
2007-03-29drm/bo: avoid oops if the memory manager for this type isn't initialisedDave Airlie
2007-03-29nouveau: fix nv04 context switches.Stephane Marchesin
2007-03-27drm/i915: set the bo up at firstopen time not after DMA initDave Airlie
This is required to use TTM to allocate the ring buffer.
2007-03-27drm/ttm: make sure dev_mapping is set-up for the first opener of the drmDave Airlie
This was causing an oops in my miniglx code to try and use a TTM-only setup.
2007-03-27Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestlineNian Wu
2007-03-26nouveau: move card initialisation into the drmBen Skeggs
The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-25Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestlineNian Wu
2007-03-24Catch up to new interrupt API, and retire FreeBSD 4.x support here.Eric Anholt
2007-03-24vm: cleanup drm_vm.c along lines of cleanups queued for kernelDave Airlie
2007-03-23Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestlineNian Wu
2007-03-23nouveau: rework nouveau_fifo_alloc() so the drm can create internal FIFOsBen Skeggs
2007-03-23cleanup more whitespace from ttm mergeDave Airlie
2007-03-23drm: remove second spinlock init for tasklet lockDave Airlie
2007-03-23nouveau: remove unused cruftBen Skeggs
2007-03-21Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestlineNian Wu
2007-03-21nouveau: support multiple channels per client (breaks drm interface)Ben Skeggs
2007-03-20Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestlineNian Wu
2007-03-20rename badly named defineDave Airlie
2007-03-19remove i830 referenceAlan Hourihane
2007-03-19Remove old i830 kernel driver.Alan Hourihane
2007-03-19Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestlineNian Wu
2007-03-19more return values fixupDave Airlie
2007-03-19fixup return values in drm ioctlDave Airlie
2007-03-19more whitespace issuesDave Airlie
2007-03-19cleanup ioctl expansion codeDave Airlie
2007-03-19oops missing elseDave Airlie
2007-03-19make drm fops const from kernelDave Airlie
2007-03-19use ARRAY_SIZEDave Airlie
2007-03-19more tab/space conversionDave Airlie
2007-03-19whitespace cleanup pending a kernel mergeDave Airlie
2007-03-19clean up more of inline functions agp_remap/drm_lookup_mapDave Airlie
2007-03-18deinline agp_remap along lines of kernelDave Airlie
2007-03-18remove drm_lookup_map unused nowDave Airlie
2007-03-14Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestlineNian Wu
2007-03-13r300: Renamed the CACHE_CTLSTAT values to include UNKNOWN in the name; notOliver McFadden
enough information is known about them to be sure as to what the values mean.
2007-03-13Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestlineNian Wu
2007-03-13Add defines for the values written to R300_RB3D_ZCACHE_CTLSTAT.Oliver McFadden
Note that just like the values written to R300_RB3D_DSTCACHE_CTLSTAT these values are really unknown; ideally more reverse engineering should be done to determine what these values mean and when they should be set.
2007-03-13nouveau: make sure cmdbuf object gets destroyedBen Skeggs
2007-03-13nouveau: associate all created objects with a channel + cleanupsBen Skeggs
2007-03-13nouveau: s/fifo/channel/Ben Skeggs
2007-03-13Corrected values written to R300_RB3D_DSTCACHE_CTLSTAT to eitherOliver McFadden
R300_RB3D_DSTCACHE_02 or R300_RB3D_DSTCACHE_0A, rather than hexadecimal values.
2007-03-13Guess another unknown register used for R300 pacification.Oliver McFadden
2007-03-12Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestlineNian Wu
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