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This is required to use TTM to allocate the ring buffer.
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This was causing an oops in my miniglx code to try and use a TTM-only setup.
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The PGRAPH init for the various cards will need cleaning up at some point,
a lot of the values written there are per-context state left over from the
all the hardcoding done in the ddx.
It's possible some cards get broken by this commit, let me know.
Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
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enough information is known about them to be sure as to what the values mean.
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Note that just like the values written to R300_RB3D_DSTCACHE_CTLSTAT these
values are really unknown; ideally more reverse engineering should be done to
determine what these values mean and when they should be set.
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R300_RB3D_DSTCACHE_02 or R300_RB3D_DSTCACHE_0A, rather than hexadecimal values.
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This is precursor to getting a TTM backend for this stuff, and also
allows the PCI table to be allocated at fb 0
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