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2012-04-11modetest: fix typoRob Clark
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rob Clark <rob@ti.com>
2012-04-03modetest: add AR15/XR15 (RGB-1555) formatsRob Clark
Signed-off-by: Rob Clark <rob@ti.com>
2012-04-03modetest: add YUV and multi-planar supportRob Clark
Signed-off-by: Rob Clark <rob@ti.com>
2012-04-03modetest: add drm_plane supportRob Clark
Signed-off-by: Rob Clark <rob@ti.com>
2012-04-03omap: fix compiler warningVíctor Manuel Jáquez Leal
When compiling with linaro toolchain version 4.6.2 got this warning. CC omap_drm.lo omap_drm.c: In function 'omap_bo_new_impl': omap_drm.c:139:6: warning: 'bo' may be used uninitialized in this function [-Wuninitialized] This patch initialize bo to NULL avoiding the warning. Signed-off-by: Víctor Manuel Jáquez Leal <vjaquez@igalia.com> Signed-off-by: Rob Clark <rob@ti.com>
2012-04-03omap: fix license headerRob Clark
In syncing with the corresponding kernel header, the wrong license header was inadvertantly copied over. The intention was for the userspace headers to have a MIT license following the convention of the rest of libdrm, xorg, etc. Signed-off-by: Rob Clark <rob@ti.com>
2012-04-02intel/decode: decode MI_WAIT_FOR_EVENTDaniel Vetter
... and add support to decode MI instructions with functions. Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-04-01intel: add Ivy Bridge GT2 server variantEugeni Dodonov
We were missing this one and it is being used by Bromolow. Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
2012-03-28configure: Bump version for 2.4.33Alex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2012-03-28omap: add omapdrm supportRob Clark
This adds libdrm_omap helper layer (as used by xf86-video-omap, omapdrmtest, etc). Signed-off-by: Rob Clark <rob@ti.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> [danvet: pushed for Rob, he doesn't yet have commit access.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-03-22intel: Add some PCI IDs for Haswell.Kenneth Graunke
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
2012-03-20radeon: add TN surface supportAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-03-16configure: Bump version for 2.4.32.Eric Anholt
2012-03-13intel: Quiet two more valgrind complaints with recent changes.Eric Anholt
These are more cases where valgrind doesn't understand what gets read or written by our ioctls.
2012-03-10intel: Add per-dword decode of gen7 3DPRIMITIVE.Eric Anholt
2012-03-10intel: Move the gen4-6 3DPRIMITIVE handling out of the switch statement.Eric Anholt
2012-03-10intel: Add support for (possibly) unsynchronized maps.Eric Anholt
This improves the performance of Mesa's GL_MAP_UNSYNCHRONIZED_BIT path in GL_ARB_map_buffer_range. Improves Unigine Tropics performance at 1024x768 by 2.30482% +/- 0.0492146% (n=61) v2: Fix comment grammar. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-03-09intel: Fix error check for I915_PARAM_HAS_LLC.Eric Anholt
drmIoctl returns -1 on error with errno set to the error value. Other users of it in this file just check for != 0, and only use errno when they need to send an error value on to the caller of the API.
2012-03-09intel: Bump the copyright dates on the bufmgr files.Eric Anholt
We've been hacking these constantly.
2012-03-09intel: Add .aub file output support.Eric Anholt
This will allow the driver to capture all of its execution state to a file for later debugging. intel_gpu_dump is limited in that it only captures batchbuffers, and Mesa's captures, while more complete, still capture only a portion of the state involved in execution. This is a squash commit of a long series of hacking as we tried to get the resulting traces to work in the internal simulator. It contains contributions by Yuanhan Liu and Kenneth Graunke. v2: Drop the MI_FLUSH_ENABLE setup. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2012-03-09intel: Add support for overriding the PCI ID via an environment variableKenneth Graunke
For example: export INTEL_DEVID_OVERRIDE=0x162 If this variable is set, don't actually submit the batchbuffer to the GPU, it probably contains commands for the wrong generation of hardware. v2: Introduce a getter for the overridden devid, and avoid getenv per exec. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2012-03-09xf86drmMode.h: Add header protectionDavid Herrman
xf86drmMode.h is missing a header protection. xf86drm.h has one so just copy it and adjust the name. Reviewed-by: Adam Jackson <ajax@redhat.com> Signed-off-by: David Herrmann <dh.herrmann@googlemail.com>
2012-03-05Make drm/drm_fourcc.h portable to non-linux platformsAlan Coopersmith
Signed-off-by: Alan Coopersmith <alan.coopersmith@oracle.com>
2012-03-02Don't require pciaccess if Intel is disabledMatt Turner
Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Matt Turner <mattst88@gmail.com>
2012-02-22intel: Import a new batchbuffer for the gen7 test.Eric Anholt
This one doesn't have the 3DSTATE_HIER_DEPTH_BUFFER bug that the previous one did. Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-02-22intel: Add decode for gen7 HIER_DEPTH_BUFFER.Eric Anholt
Note that the regression test complains here: The batch that was captured included a bug in its packet output, which was later fixed in Mesa. Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-02-22intel: Add decode for gen7 3DSTATE_WM.Eric Anholt
This requires pulling the gen6 3DSTATE_WM out to a function so it doesn't override gen7's handler. v2: Fix pasteo in interpreting ZW interpolation (thanks danvet!). Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-02-22intel: Fix a typo in decode error message.Eric Anholt
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-02-15intel: Detect cache domain inconsistency with valgrindChris Wilson
Every access to either the GTT or CPU pointer is supposed to be proceeded by a set_domain ioctl so that GEM is able to manage the cache domains correctly and for the following access to be coherent. Of course, some people explicitly want incoherent, non-blocking access which is going to trigger warnings by this patch but are probably better served by explicit suppression. v2: Also mark the pointers as inaccessible following the explicit unmap and implicit unmap upon return to the cache. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-02-13radeon: fix pitch alignment for scanout bufferJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-13configure: Fix pkg-config test in absence of valgrindChris Wilson
The empty string used for the not case is replaced by the default if-else clause and so causes the configure to fail in the absence of valgrind. Which is not quite what was intended. Instead use the common idiom of setting a variable depending on whether the true or false branch is taken and emit the conditional code as a second step. Reported-by: Tobias Jakobi <liquid.acid@gmx.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-02-11intel: Mark up with valgrind intrinsics to reduce false positivesChris Wilson
In particular, declare the hidden CPU mmaps to valgrind so that it knows about those memory regions. v2: Add an additional VG_CLEAR for the getparam References: https://bugs.freedesktop.org/show_bug.cgi?id=35071 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Ben Widawsky <ben@bwidawsk.net> [anholt: Ideally valgrind should just learn about the ioctls, and removing the clear for the non-valgrindified code feels risky.] Reviewed-by: Eric Anholt <eric@anholt.net>
2012-02-08radeon_cs_setup_bo: Fix accounting if caller specified write and read domains.Michel Dänzer
Only account for the write domain in that case. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=43893 . Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-02-06configure: Bump version for 2.4.31Jerome Glisse
2012-02-06radeon: add r600_pci_ids.h to header fileJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-03radeon: fix surface API for good before anyone start relying on itJerome Glisse
The mipmap level computation was wrong, we need to know the block width, height, depth of compressed texture to properly compute this. Change API to provide block width, height, depth instead of nblk_x, nblk_y, nblk_z. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-02radeon: surface fix macro -> micro tile fallbackJerome Glisse
We need to force 1D tiling only on old kernel the fallback was broken along the way. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-02Using sizeof() on a function parameter with an array type does notVille Syrjälä
work. sizeof() treats such parameters as pointers. Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
2012-02-02This function was missing.Ville Syrjälä
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
2012-02-02drmModeFreeResources() always leaked some memory.Ville Syrjälä
drmModeGetPlaneResources() and drmModeGetPlane() leaked in one error path. Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
2012-02-01radeon: add surface allocator helper v10Jerome Glisse
The surface allocator is able to build complete miptree when allocating surface for r600/r700/evergreen/northern islands GPU family. It also compute bo size and alignment for render buffer, depth buffer and scanout buffer. v2 fix r6xx/r7xx 2D tiling width align computation v3 add tile split support and fix 1d texture alignment v4 rework to more properly support compressed format, split surface pixel size and surface element size in separate fields v5 support texture array (still issue on r6xx) v6 split surface value computation and mipmap tree building, rework eg and newer computation v7 add a check for tile split and 2d tiled v8 initialize mode value before testing it in all case, reenable 2D macro tile mode on r6xx for cubemap and array. Fix cubemap to force array size to the number of face. v9 fix handling of stencil buffer on evergreen v10 on evergreen depth buffer need to have enough room for a stencil buffer just after depth one Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-01intel: query for LLC supportEugeni Dodonov
This adds support for querying the kernel about the LLC support in the hardware. In case the ioctl fails, we assume that it is present on GEN6 and GEN7. v2: fix the return code checking Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
2012-01-31intel: Fix build of Intel DRM on x86 systemsPaul Berry
Commit efd6e81e inadvertently broke the build by looking for "i?86" or "x86_64" in $host_os. The correct variable to check is $host_cpu. This was preventing libdrm_intel.so from being built. Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-01-30Don't build Intel DRM if $CHOST is not i?86-* or x86_64-*Jeremy Huddleston
This fixes a failure in 'make check' found by the tinderbox when trying to build this code on Linux/ppc. This code is only designed to run on Intel platforms, so don't even bother building it if we're not in that set. Found-by: Tinderbox Signed-off-by: Jeremy Huddleston <jeremyhu@apple.com>
2012-01-30intel: Fix bufmgr_gem->gen for gen > 4Chad Versace
If the pci_device's actual gen was > 4, then we stupidly set bufmgr_gem->gen = 6. Luckily this caused no bugs, and this fix shouldn't change any behavior, because all checks against the gen currently have one of the forms below: gen == 2 gen == 3 gen >= 4 Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2012-01-27intel: Add minimal decode for remaining gen7 packets in use.Eric Anholt
This just gets packet name and length in place, with the remainder unfinished. I've long since finished the work that got me started fixing up the decode.
2012-01-27intel: Add decode for gen7 constant buffer packets.Eric Anholt
2012-01-27intel: Add decode for gen7 state pointers.Eric Anholt
Since CC_STATE_POINTERS for gen6 and 7 are quite different but use the same opcode, move gen6 out to a helper function too, so we can use a helper function for gen7.
2012-01-27intel: Add support for parsing gen7 URB packets.Eric Anholt
2012-01-27intel: Make most of the logic for 965 3d packet length checks table-driven.Eric Anholt
This puts the error message in a consistent location relative to the packet, and while I'm here I made the error message a bit more informative. Now, most static length packets need to just declare their length in the table and not worry.
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