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2008-07-18intel-gem: Leave 8xx tiling on until we find any issues.Eric Anholt
2008-07-18radeon: remove microcode versionDave Airlie
2008-07-18drm/radeon: fixup 0 vs NULLDave Airlie
2008-07-17[FreeBSD] drm_irq.c updates for vblank fixes.Robert Noland
2008-07-17i915: remove old broken vblank codeJesse Barnes
Remove the unused (and broken) "in vblank" code now that the core has been fixed to use a counter while interrupts are enabled. Also make the vblank pipe get/set ioctls into dumb stub functions, since with the new code we can no longer let userspace control whether vblank interrupts are enabled, or the core code will misbehave.
2008-07-17Avoid incorrect vblank wakeupsJesse Barnes
The current code uses the hw vblank counter exclusively, which can lead to wakeups during the active period rather than during the vblank period if the hw counter counts displayed frames rather than vblank periods. This change coverts the code over to using the counter while interrupts are enabled, fixing that issue. It also includes a couple of related changes: one to not enable the new enable/disable behavior until the modeset ioctl is called (to preserve old client behavior) and another to account for lost events due to mode setting with the new counter scheme. BSD will require similar changes to its drm_irq.c code, but they should be straightforward.
2008-07-16FreeBSD: Fix radeon buildRobert Noland
2008-07-16BSD: change drm_locked_task*() to use the same scheme as linux.Owain Gordon Ainsworth
The current code can sleep in an interrupt handler, that is bad. So instead if we can't grab the lock, flag it and run the tasklet on unlock. Signed-off-by: Robert Noland <rnoland@2hip.net>
2008-07-15[FreeBSD] We aren't allowed to hold locks over bus_dma_tag_create or ↵Robert Noland
bus_dmamem_alloc.
2008-07-15This is a modified version of Hong's patch from last month, with a fewHong Liu
modifications to make it work correctly on my test hardware (altered the backlight write function, made it enable the legacy backlight controller interrupts on mobile hardware, sorted the interrupt function so we don't get an excessive number of vblank interrupts). This lets the backlight keys on my T61 work properly, though there's a 750msec or so delay between the request and the brightness actually changing - this sounds awfully like the hardware spinning waiting for a status flag to become ready, but as far as I can tell they're all set correctly. If anyone can figure out what's wrong here, it'd be nice to know. Some of the functions are still stubs and just tell the hardware that the request was successful. These can be filled in as kernel modesetting gets integrated. I think it's worth getting this in anyway, since it's required for backlight control to work properly on some new platforms. Signed-off-by: Matthew Garrett <mjg@redhat.com>
2008-07-15drm: fix missing symbol exportDave Airlie
2008-07-15drm: add fix for PAT on radeon with 2.6.26Dave Airlie
2008-07-15drm/pcigart: fix warningDave Airlie
2008-07-14intel-gem: Disable tiling if we get junk from the MCHBAR read.Eric Anholt
One of our systems has been returning 0xffffffff from all MCHBAR reads, which means we'll need to figure out why, or add an alternate detection method.
2008-07-11intel-gem: Add two new ioctls for managing tiling on objects.Eric Anholt
Various chips have exciting interactions between the CPU and the GPU's different ways of accessing interleaved memory, so we need some kernel assistance in determining how it works. Only fully tested on GM965 so far.
2008-07-08xgi: use true/false instead of TRUE/FALSEmartin capitanio
2008-07-08nouveau: interface changes for nv5x 3dBen Skeggs
2008-07-07[intel-gem] typo fix in DRM_ERROREric Anholt
2008-07-03i915: official name for GM45 chipsetZhenyu Wang
Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com>
2008-07-01i915: only use tiled blits on 965+Jesse Barnes
When scheduled swaps occur, we need to blit between front & back buffers. I the buffers are tiled, we need to set the appropriate XY_SRC_COPY tile bit, only on 965 chips, since it will cause corruption on pre-965 (e.g. 945). Bug reported by and fix tested by Tomas Janousek <tomi@nomi.cz>. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-07-01Revert "i915: only use tiled blits on 965+"Jesse Barnes
This reverts commit 727d4f1d1667e43b3558bd5f6ed6dc2cd9c29401, somehow git deleted the symlink and replaced it with the file.
2008-07-01i915: only use tiled blits on 965+Jesse Barnes
When scheduled swaps occur, we need to blit between front & back buffers. If the buffers are tiled, we need to set the appropriate XY_SRC_COPY tile bit, but only on 965 chips, since it will cause corruption on pre-965 (e.g. 945). Bug reported by and fix tested by Tomas Janousek <tomi@nomi.cz>. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-07-01i915: enable bus mastering on i915 at resume timeJie Luo
On 9xx chips, bus mastering needs to be enabled at resume time for much of the chip to function. With this patch, vblank interrupts will work as expected on resume, along with other chip functions. Fixes kernel bugzilla #10844. Signed-off-by: Jie Luo <clotho67@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-06-25nv50: when destroying a channel make sure it's not still current on PFIFOBen Skeggs
We won't get a PFIFO context switch when the same channel ID is recreated if the hw still thinks the channel is already active, which causes fun issues. Should allow X to be stopped and started without tearing down the entire card state in lastclose().
2008-06-24[intel] Get vblank pipe from irq_mask_reg instead of hardware enable regKeith Packard
With the interrupt enable/disable using only the mask register, it was wrong to use the enable register to detect which pipes had vblank detection turned on. Also, as we keep a local copy of the mask register around, and MSI machines smack the hardware during the interrupt handler, it is more efficient and more correct to use the local copy.
2008-06-24[intel] Create functions to enable/disable interruptsKeith Packard
This shares common code sequences for managing the interrupt register bits
2008-06-24i915: remove unused variableJesse Barnes
Leftover dev_priv from the move of the suspend/resume code into shared-core.
2008-06-24i915: register definition & header file cleanupJesse Barnes
It would be nice if one day the DRM driver was the canonical source for register definitions and core macros. To that end, this patch cleans things up quite a bit, removing redundant definitions (some with different names referring to the same register) and generally tidying up the header file.
2008-06-24Merge branch 'drm-gem' into drm-gem-965Keith Packard
2008-06-24[intel-gem] Include drm_compat.h to get kmap_atomic_prot_pfnKeith Packard
2008-06-24drm_compat: it's CONFIG_HIGHMEM, not CONFIG_HIMEMKeith Packard
A mis-spelled config option (was it spelled that way in the past?) eliminated kmap_atomic_prot_pfn from core DRM.
2008-06-24[intel-gem] Use I915_GEM_DOMAIN_GTT in dri_gem_bo_wait_rendering.Keith Packard
I915_GEM_DOMAIN_CPU is very expensive to wait for -- it generally requires clflushing the frame buffer.
2008-06-24[intel-gem] Recover resources from wedged hardware.Keith Packard
Clean up queues, free objects. On the next entervt, unmark the hardware to let the user try again (presumably after resetting the chip). Someday we'll automatically recover...
2008-06-24[intel-gem] pwrite through GTTKeith Packard
Pin/copy_from_user/unpin through the GTT to eliminate clflush costs. Benchmarks say this helps quite a bit.
2008-06-24Was using irq_enable_reg in the use_mask_reg pathKeith Packard
2008-06-23[intel-gem] Include drm_compat.h to get kmap_atomic_prot_pfnKeith Packard
2008-06-23drm_compat: it's CONFIG_HIGHMEM, not CONFIG_HIMEMKeith Packard
A mis-spelled config option (was it spelled that way in the past?) eliminated kmap_atomic_prot_pfn from core DRM.
2008-06-23[intel-gem] Use I915_GEM_DOMAIN_GTT in dri_gem_bo_wait_rendering.Keith Packard
I915_GEM_DOMAIN_CPU is very expensive to wait for -- it generally requires clflushing the frame buffer.
2008-06-23[intel] leave interrupts disabled in ISR only on MSI againKeith Packard
While debugging the 915, I tried this trick there and accidentally left it set.
2008-06-23[intel-gem] Recover resources from wedged hardware.Keith Packard
Clean up queues, free objects. On the next entervt, unmark the hardware to let the user try again (presumably after resetting the chip). Someday we'll automatically recover...
2008-06-23[intel] Switch to using IMR instead of IERKeith Packard
2008-06-23[intel-gem] pwrite through GTTKeith Packard
Pin/copy_from_user/unpin through the GTT to eliminate clflush costs. Benchmarks say this helps quite a bit.
2008-06-23[intel] allow the irq code to use either enable or mask registersKeith Packard
still not sure which works best on which hardware; this will make it easier to experiment.
2008-06-23nv50: oops, keep VRAM allocations aligned at 64KiB - that's our page size..Ben Skeggs
2008-06-23nv50: use same dma object for fb/tt accessBen Skeggs
We depend on the VM fully now for memory protection, separate DMA objects for VRAM and GART are unneccesary. However, until the next interface break (soon) a client can't depend on the objects being the same and must still call NV_OBJ_SET_DMA_* methods appropriately.
2008-06-23nouveau: allocate drm-use vram buffers from end of vram.Ben Skeggs
This avoids seeing garbage from engine setup etc before X gets around to pointing the CRTCs at a new scanout buffer. Not actually a noticable problem before G80 as PRAMIN is forced to the end of VRAM by the hardware already.
2008-06-22agp: use true/false instead of TRUE/FALSEDave Airlie
2008-06-21RADEON: 0x1002 0x5657 is actually an RV410Alex Deucher
See bug 14289
2008-06-21[intel] Use IMR instead of IER to pend interrupts during ISRKeith Packard
Noting that the interrupt mask register was more reliable than the interrupt enable register for managing interrupts in user_irq_on/user_irq_off, this patch replaces the remaining IER frobbing with IMR instead. The test which exposes IER related failures is: $ glxgears & glxgears & glxgears (reposition the glxgears windows away from the upper left corner) $ while :; do x11perf -rect100 -reps 800 -repeat 1; sleep 1; done & $ while :; do runoa; runet; done &
2008-06-21[intel-gem] Add /proc/dri/*/i915_gem_interruptKeith Packard
This tracks most of the interrupt-related status, including the interrupt registers in the chip and the sequence number variables.