| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2008-05-21 | [gem] Hold a reference on the object in i915_gem_wait_space. | Eric Anholt | |
| Otherwise, in the middle of the function called using it the last ref might disappear. | |||
| 2008-05-21 | [intel-gem] invalidate ring locals for pin/unpin/set_domain/free functions | Keith Packard | |
| Ring locals must be reloaded from hardware in case the X server ran. | |||
| 2008-05-21 | rs690/r500: vblank support. | Dave Airlie | |
| The new display controller has the vblank interrupts in a different place. Add support for vbl interrupts for these chips | |||
| 2008-05-20 | [gem] Use a separate sequence number field from classic/ttm | Eric Anholt | |
| This lets us get some qualities we desire, such as using the full 32-bit range (except zero), avoiding DRM_WAIT_ON, and a 1:1 mapping of active sequence numbers to request structs, which will be used soon for throttling and interrupt-driven list cleanup. | |||
| 2008-05-20 | [gem] Rename sequence numbers from "cookie" to "seqno" | Eric Anholt | |
| 2008-05-20 | [gem] Clean up active/inactive list handling using helper functions. | Eric Anholt | |
| Additionally, a boolean active field is added to indicate which list an object is on, rather than smashing last_rendering_cookie to 0 to show inactive. This will help with flush-reduction later on, and makes the code clearer. | |||
| 2008-05-17 | r500: add more register ranges for Mesa driver | Dave Airlie | |
| 2008-05-15 | [gem] Hold dev->struct_mutex to protect structure data. | Eric Anholt | |
| 2008-05-15 | [gem] Rename the GTT LRU lists to active (executing) and inactive (idle). | Eric Anholt | |
| 2008-05-15 | [gem] typo fix in comment. | Eric Anholt | |
| 2008-05-14 | ati_pcigart: oops wrong way around not that it actually mattered | Dave Airlie | |
| 2008-05-14 | ati_pcigart: stop working in the evenings you mess up too often | Dave Airlie | |
| 2008-05-14 | Revert "ati_pcigart: fixup properly this version might even work" | Dave Airlie | |
| This reverts commit bc0836e12a9790f1cc83f8bc29bc05043c4bc840. tree has some kref hacks in it - oops | |||
| 2008-05-14 | ati_pcigart: fixup properly this version might even work | Dave Airlie | |
| 2008-05-14 | ati_pcigart: fill out 40-bit gart table support properly | Dave Airlie | |
| Thanks to Alex for supplying this info. | |||
| 2008-05-13 | RS4xx: separate out RS400 and RS480 IGP chips | Alex Deucher | |
| RS400 (intel based IGP) and RS480 (AMD based IGP) have different MC and GART setups. Currently we only support RS480. | |||
| 2008-05-12 | [GEM] Update testcases for new API. | Eric Anholt | |
| 2008-05-12 | [GEM] Typo (and thinking) fixes in drm-gem.txt and doxygen. | Eric Anholt | |
| 2008-05-12 | [intel] Minor kludge -- wait for the ring to be nearly empty before queuing | Keith Packard | |
| No need to fill the ring that much; wait for it to become nearly empty before adding the execbuffer request. A better fix will involve scheduling ring insertion in the irq handler. | |||
| 2008-05-12 | [intel] When polling for ring space, sleep for a lot longer (10ms) | Keith Packard | |
| If the ring is full, the engine will surely be running for more than 10ms. | |||
| 2008-05-12 | [gem] Set write domain to CPU when doing pwrite. | Keith Packard | |
| Leave the flush call in place, which can fix domains up if necessary. | |||
| 2008-05-12 | [gem] Clarify use of explicit domain control. Remove Gen3 from I-cache usage. | Keith Packard | |
| 2008-05-12 | RADEON: fix copy/pasto in last commit | Alex Deucher | |
| 2008-05-12 | R3/4/5: init pipe setup in drm | Alex Deucher | |
| Similar (broken) code in mesa needs to be removed | |||
| 2008-05-12 | RADEON: cleanup radeon_do_engine_reset() | Alex Deucher | |
| 2008-05-12 | R300+: fixup pixcache flush | Alex Deucher | |
| 2008-05-12 | RS4xx: fix MCIND index mask | Alex Deucher | |
| 2008-05-12 | RADEON: write AGP_BASE_2 on chips that support it | Alex Deucher | |
| 2008-05-12 | R300+: fixup PURGE/FLUSH macros | Alex Deucher | |
| 2008-05-12 | Radeon IGP: merge RS4xx/RS6xx gart setup | Alex Deucher | |
| 2008-05-12 | Radeon IGP: wrap MCIND access | Alex Deucher | |
| first step in merging rs4xx/rs6xx gart setup | |||
| 2008-05-12 | Radeon IGP: clean up registers and magic numbers | Alex Deucher | |
| 2008-05-11 | [GEM] Make pread/pwrite manage memory domains. No luck with movnti though. | Keith Packard | |
| pread and pwrite must update the memory domains to ensure consistency with the GPU. At some point, it should be possible to avoid clflush through this path, but that isn't working for me. | |||
| 2008-05-10 | [intel-GEM] exec list can contain pinned, lru cannot. | Keith Packard | |
| The exec list contains all objects, in order of use. The lru list contains only unpinned objects ready to be evicted. This required two changes -- the first was to not migrate pinned objects from exec to lru, the second was to search for the first unpinned object in the exec list when doing eviction. | |||
| 2008-05-10 | Merge commit 'anholt/drm-gem' into drm-gem | Keith Packard | |
| 2008-05-10 | [GEM] Add drm-gem.txt | Keith Packard | |
| Add some API and implementation documentation for GEM. | |||
| 2008-05-10 | [intel-GEM] Clean up GEM ioctl naming. | Keith Packard | |
| Rename 'validate_entry' to 'exec_object', then clean up some field names in structures (renaming buffer_offset to just offset, for example). | |||
| 2008-05-09 | GEM: Fix arguments to drm_memrange_init so we don't exceed our allocation. | Eric Anholt | |
| It takes (offset, size), not (offset, end). | |||
| 2008-05-09 | GEM: Separate the LRU into execution list and LRU list. | Eric Anholt | |
| Now, the LRU list has objects that are completely done rendering and ready to kick out, while the execution list has things with active rendering, which have associated cookies and reference counts on them. | |||
| 2008-05-09 | GEM: Clear obj_priv->agp_mem when we free it. | Eric Anholt | |
| Still managing to get something wrong with this, oopsing down in agp. | |||
| 2008-05-09 | GEM: Avoid leaking refs on target objects on presumed offset success. | Eric Anholt | |
| 2008-05-09 | [gem] API cleanup. allocate->create unreference->close name->flink | Keith Packard | |
| Make the API names a bit more consistent. | |||
| 2008-05-08 | [i915] clean up whinging from checkpatch.pl | Keith Packard | |
| 2008-05-08 | Clean up whinging from checkpatch.pl in drm_gem.c | Keith Packard | |
| Whitespace changes, a few too-long-lines and some extra braces. | |||
| 2008-05-08 | GEM: Fix oops on NULL dereference when we try clflushing when we don't need to. | Eric Anholt | |
| 2008-05-08 | [intel-gem] Move domains to relocation records. add set_domain ioctl. | Keith Packard | |
| Domain information is about buffer relationships, not buffer contents. That means a relocation contains the domain information as it knows how the source buffer references the target buffer. This also adds the set_domain ioctl so that user space can move buffers to the cpu domain. | |||
| 2008-05-07 | GEM: fix testcases for new ioctl args. | Eric Anholt | |
| 2008-05-07 | Apply a few stylistic cleanups to match kernel code. | Arjan van de Ven | |
| 2008-05-07 | GEM: Wait for existing rendering to complete before writing relocation data. | Eric Anholt | |
| This should already have been generally safe since we don't change contents and put in new relocations between execbufs, so if we were writing in a new relocation then we'd already waited rendering to complete when we moved the target of the relocation. However, doing the right thing will be required if we do buffer reuse. | |||
| 2008-05-07 | GEM: Extend cache domain stuff for 965. | Eric Anholt | |
| One of our MI_FLUSH bits is reserved on 965, being always implied, and there's a vertex cache that was forgotten. | |||
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index : renesas/drm.git | |
| libdrm, cloned from git://anongit.freedesktop.org/mesa/drm | Laurent Pinchart |
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