Age | Commit message (Collapse) | Author |
|
|
|
It looks like 'after a while', I915REG_INT_IDENTITY_R for some reason always has
VSYNC_PIPEB_FLAG set in the interrupt handler, even though pipe B is disabled.
So we only increase dev->vbl_received if the corresponding bit is also set in
dev->vblank_pipe.
(cherry picked from 881ba569929ceafd42e3c86228b0172099083d1d commit)
|
|
(cherry picked from 2627131e5d0c8cd5e3f0db06451c2e7ae7569b1b commit)
|
|
(cherry picked from 0356fe260dcf80f6d2d20e3384f2a1f4ee7f5b30 commit)
|
|
(cherry picked from 50a0284a61d4415c0ebdb02decee76ef3115007a commit)
|
|
It looks like this would have caused signals to always get sent on the next
vertical blank, regardless of the sequence number.
(cherry picked from cf6b2c5299e9be3542d4deddfd05d5811f11d2ef commit)
|
|
When this flag is set and the target sequence is missed, wait for the next
vertical blank instead of returning immediately.
(cherry picked from 89e323e4900af84cc33219ad24eb0b435a039d23 commit)
|
|
(cherry picked from 7f09f957d9a61ac107f8fd29128d7899a3e8a228 commit)
|
|
(cherry picked from c2bdb76814755c9ac6e66a8815f23af0fe4f3a91 commit)
|
|
(cherry picked from 84b38b63f05e04ade8b1ddfb770047fd86de0d64 commit)
|
|
Initialize it to default value if it hasn't been set by the X server yet.
In i915_vblank_pipe_set(), only update dev_priv->vblank_pipe and call
i915_enable_interrupt() if the argument passed from userspace is valid to avoid
corrupting dev_priv->vblank_pipe on invalid arguments.
(cherry picked from 87c57cba1a70221fc570b253bf3b24682ef6b894 commit)
|
|
Handle relative as well as absolute target sequence numbers.
Return error if target sequence has already passed, so userspace can deal with
this situation as it sees fit.
On success, return the sequence number of the vertical blank when the buffer
swap is expected to take place.
Also add DRM_IOCTL_I915_VBLANK_SWAP definition for userspace code that may want
to use ioctl() instead of drmCommandWriteRead().
(cherry picked from d5a0f107511e128658e2d5e15bd7e6215c507f29 commit)
|
|
This makes it easier for userspace to know when it needs to allocate an ID.
Also free drawable information memory when it's no longer needed.
(cherry picked from df7551ef7334d728ec0371423661bb403d3e270a commit)
|
|
(cherry picked from d04751facea36cb888c7510b126658fdbc4277d5 commit)
|
|
This uses the core facility to schedule a driver callback that will be called
ASAP after the given vertical blank interrupt with the HW lock held.
(cherry picked from 257771fa290b62d4d2ad896843cf3a207978d0bb commit)
|
|
(cherry picked from 23d2833aaa37a33b9ddcf06cc796f59befc0d360 commit)
|
|
(cherry picked from b9f3009160d8bd1a26a77d6f1616f1679c7b969d commit)
|
|
(cherry picked from 43f8675534c7e95efbc92eaf2c8cc43aef95f125 commit)
|
|
(cherry picked from 98a89504589427a76c3f5cfa2266962a1a212672 commit)
|
|
Also improve diagnostic output.
(cherry picked from af48be1096221d551319c67a9e782b50ef58fefd commit)
|
|
Actually make the existing ioctls for adding and removing drawables do
something useful, and add another ioctl for the X server to update drawable
information. The only kind of drawable information tracked so far is cliprects.
(cherry picked from 29598e5253ff5c085ccf63580fd24b84db848424 commit)
|
|
(cherry picked from d817cc1f30060fcc4a85a05b2de8a2a1687421b5 commit)
|
|
When the vertical blank interrupt is enabled for both pipes, pipe A is
considered primary and pipe B secondary. When it's only enabled for one pipe,
it's always considered primary for backwards compatibility.
(cherry picked from 0c7d7f43610f705e8536a949cf2407efaa5ec217 commit)
|
|
(cherry picked from ab351505f36a6c66405ea7604378268848340a42 commit)
|
|
Fix up some comments.
|
|
Prepare for the possibility to evict all buffers from vram / agp.
This will be used by the X server when, for example, switching vts.
|
|
This fixes issues on X server startup with versions of xf86-video-intel that
enable the IRQ before they have a context ID.
|
|
It looks like 'after a while', I915REG_INT_IDENTITY_R for some reason always has
VSYNC_PIPEB_FLAG set in the interrupt handler, even though pipe B is disabled.
So we only increase dev->vbl_received if the corresponding bit is also set in
dev->vblank_pipe.
|
|
|
|
|
|
|
|
It looks like this would have caused signals to always get sent on the next
vertical blank, regardless of the sequence number.
|
|
When this flag is set and the target sequence is missed, wait for the next
vertical blank instead of returning immediately.
|
|
|
|
|
|
|
|
Initialize it to default value if it hasn't been set by the X server yet.
In i915_vblank_pipe_set(), only update dev_priv->vblank_pipe and call
i915_enable_interrupt() if the argument passed from userspace is valid to avoid
corrupting dev_priv->vblank_pipe on invalid arguments.
|
|
Handle relative as well as absolute target sequence numbers.
Return error if target sequence has already passed, so userspace can deal with
this situation as it sees fit.
On success, return the sequence number of the vertical blank when the buffer
swap is expected to take place.
Also add DRM_IOCTL_I915_VBLANK_SWAP definition for userspace code that may want
to use ioctl() instead of drmCommandWriteRead().
|
|
This makes it easier for userspace to know when it needs to allocate an ID.
Also free drawable information memory when it's no longer needed.
|
|
|
|
This uses the core facility to schedule a driver callback that will be called
ASAP after the given vertical blank interrupt with the HW lock held.
|
|
|
|
|
|
|
|
|
|
Also improve diagnostic output.
|
|
Actually make the existing ioctls for adding and removing drawables do
something useful, and add another ioctl for the X server to update drawable
information. The only kind of drawable information tracked so far is cliprects.
|
|
|
|
When the vertical blank interrupt is enabled for both pipes, pipe A is
considered primary and pipe B secondary. When it's only enabled for one pipe,
it's always considered primary for backwards compatibility.
|
|
|