| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2008-06-27 | NV50: use list_head item instead of list_head head to avoid confusion | Maarten Maathuis | |
| 2008-06-27 | Change some obviously wrong things about property blobs, still broken though. | Maarten Maathuis | |
| - I do not fully understand these blobs, so i'm leaving it at this for the moment. | |||
| 2008-06-27 | [modesetting-101] Actually store properties when being changed. | Maarten Maathuis | |
| 2008-06-27 | NV50: A minor change. | Maarten Maathuis | |
| 2008-06-27 | NV50: Implement DPMS. | Maarten Maathuis | |
| 2008-06-26 | [modesetting-101] tab-cleanup | Maarten Maathuis | |
| 2008-06-26 | Revert "modesetting-101: Make dpms property optional + misc cleanup." | Maarten Maathuis | |
| This reverts commit 13943fe5823c45759091c1a1f487a4abe377421e. | |||
| 2008-06-26 | modesetting-101: Make dpms property optional + misc cleanup. | Maarten Maathuis | |
| - intel_crt seems the only one to provide it, so init it there. | |||
| 2008-06-25 | NV50: i misunderstood NOUVEAU_MEM_INTERNAL, so remove it | Maarten Maathuis | |
| 2008-06-25 | NV50: Some cleanup and fixes. | Maarten Maathuis | |
| 2008-06-25 | nv50: when destroying a channel make sure it's not still current on PFIFO | Ben Skeggs | |
| We won't get a PFIFO context switch when the same channel ID is recreated if the hw still thinks the channel is already active, which causes fun issues. Should allow X to be stopped and started without tearing down the entire card state in lastclose(). | |||
| 2008-06-25 | nouveau: allocate drm-use vram buffers from end of vram. | Ben Skeggs | |
| This avoids seeing garbage from engine setup etc before X gets around to pointing the CRTCs at a new scanout buffer. Not actually a noticable problem before G80 as PRAMIN is forced to the end of VRAM by the hardware already. | |||
| 2008-06-24 | silence warning | root | |
| 2008-06-24 | [intel] Get vblank pipe from irq_mask_reg instead of hardware enable reg | Keith Packard | |
| With the interrupt enable/disable using only the mask register, it was wrong to use the enable register to detect which pipes had vblank detection turned on. Also, as we keep a local copy of the mask register around, and MSI machines smack the hardware during the interrupt handler, it is more efficient and more correct to use the local copy. | |||
| 2008-06-24 | [intel] Create functions to enable/disable interrupts | Keith Packard | |
| This shares common code sequences for managing the interrupt register bits | |||
| 2008-06-24 | NV50: minor change | Maarten Maathuis | |
| 2008-06-24 | Merge branch 'drm-gem' into drm-gem-965 | Keith Packard | |
| 2008-06-24 | [intel-gem] Include drm_compat.h to get kmap_atomic_prot_pfn | Keith Packard | |
| 2008-06-24 | drm_compat: it's CONFIG_HIGHMEM, not CONFIG_HIMEM | Keith Packard | |
| A mis-spelled config option (was it spelled that way in the past?) eliminated kmap_atomic_prot_pfn from core DRM. | |||
| 2008-06-24 | [intel-gem] Use I915_GEM_DOMAIN_GTT in dri_gem_bo_wait_rendering. | Keith Packard | |
| I915_GEM_DOMAIN_CPU is very expensive to wait for -- it generally requires clflushing the frame buffer. | |||
| 2008-06-24 | [intel-gem] Recover resources from wedged hardware. | Keith Packard | |
| Clean up queues, free objects. On the next entervt, unmark the hardware to let the user try again (presumably after resetting the chip). Someday we'll automatically recover... | |||
| 2008-06-24 | [intel-gem] pwrite through GTT | Keith Packard | |
| Pin/copy_from_user/unpin through the GTT to eliminate clflush costs. Benchmarks say this helps quite a bit. | |||
| 2008-06-24 | Was using irq_enable_reg in the use_mask_reg path | Keith Packard | |
| 2008-06-24 | NV50: fix a few misc things | Maarten Maathuis | |
| 2008-06-24 | NV50: fix cursor hide/show | Maarten Maathuis | |
| 2008-06-24 | NV50: These are actually errors. | Maarten Maathuis | |
| 2008-06-23 | [intel-gem] Include drm_compat.h to get kmap_atomic_prot_pfn | Keith Packard | |
| 2008-06-23 | drm_compat: it's CONFIG_HIGHMEM, not CONFIG_HIMEM | Keith Packard | |
| A mis-spelled config option (was it spelled that way in the past?) eliminated kmap_atomic_prot_pfn from core DRM. | |||
| 2008-06-24 | NV50: fix some misc bugs | Maarten Maathuis | |
| 2008-06-23 | [modesetting-101] update mode count after fill_modes. | Maarten Maathuis | |
| - This avoids returning with a mode count of 0, thus not allocating space for the 2nd ioctl. | |||
| 2008-06-23 | libdrm: check for allocation failure | Maarten Maathuis | |
| 2008-06-23 | NV50: Improve set_config and fix some minor bugs. | Maarten Maathuis | |
| 2008-06-23 | [intel-gem] Use I915_GEM_DOMAIN_GTT in dri_gem_bo_wait_rendering. | Keith Packard | |
| I915_GEM_DOMAIN_CPU is very expensive to wait for -- it generally requires clflushing the frame buffer. | |||
| 2008-06-23 | [intel] leave interrupts disabled in ISR only on MSI again | Keith Packard | |
| While debugging the 915, I tried this trick there and accidentally left it set. | |||
| 2008-06-23 | [intel-gem] Recover resources from wedged hardware. | Keith Packard | |
| Clean up queues, free objects. On the next entervt, unmark the hardware to let the user try again (presumably after resetting the chip). Someday we'll automatically recover... | |||
| 2008-06-23 | [intel] Switch to using IMR instead of IER | Keith Packard | |
| 2008-06-23 | [intel-gem] pwrite through GTT | Keith Packard | |
| Pin/copy_from_user/unpin through the GTT to eliminate clflush costs. Benchmarks say this helps quite a bit. | |||
| 2008-06-23 | [intel] allow the irq code to use either enable or mask registers | Keith Packard | |
| still not sure which works best on which hardware; this will make it easier to experiment. | |||
| 2008-06-22 | nouveau: disable KMS for pre-NV50 even when specifically enabled | Maarten Maathuis | |
| 2008-06-22 | NV50: Fix a few more possible leaks. | Maarten Maathuis | |
| 2008-06-22 | fix typo | Maarten Maathuis | |
| 2008-06-22 | NV50: A few minor added safeties + cleanup. | Maarten Maathuis | |
| 2008-06-22 | Undo something i didn't want to change. | Maarten Maathuis | |
| - I made it consistent with recent kernel fb code (maybe this is older bugged code?) - Still i don't use this and i should leave it to others. | |||
| 2008-06-22 | NV50: Initial import of kernel modesetting. | Maarten Maathuis | |
| 2008-06-21 | [intel] Use IMR instead of IER to pend interrupts during ISR | Keith Packard | |
| Noting that the interrupt mask register was more reliable than the interrupt enable register for managing interrupts in user_irq_on/user_irq_off, this patch replaces the remaining IER frobbing with IMR instead. The test which exposes IER related failures is: $ glxgears & glxgears & glxgears (reposition the glxgears windows away from the upper left corner) $ while :; do x11perf -rect100 -reps 800 -repeat 1; sleep 1; done & $ while :; do runoa; runet; done & | |||
| 2008-06-21 | [intel-gem] Add /proc/dri/*/i915_gem_interrupt | Keith Packard | |
| This tracks most of the interrupt-related status, including the interrupt registers in the chip and the sequence number variables. | |||
| 2008-06-21 | [intel] Count received interrupts | Keith Packard | |
| Another patch adds this to a /proc/dri file for debugging and monitoring. | |||
| 2008-06-21 | [intel-gem] Remove unused variable. | Keith Packard | |
| 2008-06-20 | [intel-gem] Use polling in i915_gem_idle instead of interrupts. | Keith Packard | |
| While waiting for the hardware to idle on leavevt or lastclose, poll for the sync sequence number instead of waiting for an interrupt. This allows the code to bail if the hardware hangs for some reason. Also, this avoids issues with signals as the exisiting wait function is interruptible. | |||
| 2008-06-20 | [intel-gem] Add intel-specific /proc entries to help monitor gem operation | Keith Packard | |
| This adds gem_active, gem_flushing, gem_inactive, gem_request and gem_seqno entries to monitor gem operation and help debug issues. | |||
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index : renesas/drm.git | |
| libdrm, cloned from git://anongit.freedesktop.org/mesa/drm | Laurent Pinchart |
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