renesas/drm.git - libdrm, cloned from git://anongit.freedesktop.org/mesa/drm

Age	Commit message (Collapse)	Author
2007-11-18	Bug #13233: Chase move of agp headers on FreeBSD.	Robert Noland

2007-11-18	radeon: refactor out the fb/agp location read/write.	Dave Airlie
	Add a new get param to get the fb location into userspace. Mesa currently hits MMIO to do this, but this isn't always possible.
2007-11-16	Fix connection status ABI	Jesse Barnes
	Userspace expects a 1 based enum for connection status so fix up the kernel definition.
2007-11-16	Fix typo in copy_to_user calls	Jesse Barnes
	We want to copy to card_res->modes + copied, not &card_res->modes + copied.
2007-11-16	nouveau: also mention the number of succcessfully copied bios bytes.	Stephane Marchesin

2007-11-15	nouveau: rename	Jeremy Kolb

2007-11-15	nouveau: flip buffer into gart.	Jeremy Kolb

2007-11-15	Use user copy routines for writing modes & ids back to userspace	Jesse Barnes
	Since the drm_mode_card_res structure contains user pointers, we have to use put_user and copy_to_user to write stuff out. The DRM ioctl wrapper will only take care of copying the base drm_mode_card_res struct, not the included arrays.
2007-11-15	nouveau: be verbose about PPC bios for now.	Stephane Marchesin

2007-11-15	nouveau: revert the nv34 context size change, it was not the culprit after all.	Stephane Marchesin

2007-11-15	nouveau: use get_property instead of of_get_property on pre-2.6.22 kernels.	Stephane Marchesin

2007-11-15	Merge branch 'master' of git+ssh://git.freedesktop.org/git/mesa/drm into ↵	Thomas Hellstrom
	modesetting-101
2007-11-15	mm fixups.	Thomas Hellstrom

2007-11-15	libdrm: return crtc id to userspace	Dave Airlie

2007-11-15	libdrm: add crtc/output ids to userspace interface	Dave Airlie

2007-11-15	drm: send correct fb id to userspace	Dave Airlie

2007-11-15	modes: pass type to userspace for preferred showing	Dave Airlie

2007-11-15	drm: don't remove mappings added by the driver	Dave Airlie

2007-11-15	intel: fixup \|\| vs \|	Dave Airlie

2007-11-15	tests: update for new drm interface	Dave Airlie

2007-11-15	Merge branch 'master' into modesetting-101	Dave Airlie
	Conflicts: shared-core/i915_dma.c tests/ttmtest/src/ttmtest.c
2007-11-15	i915: remove excess debug output	Dave Airlie

2007-11-15	nouveau: Copy the PPC bios to RAMIN on init, that lets us do proper output ↵	Stephane Marchesin
	detection in user space.
2007-11-15	intel: add flushing for i8xx chipsets.	Dave Airlie
	Add a nut vs hammer style chipset flush for the i8xx chipsets - reenable TTM code paths
2007-11-14	nouveau: nv30: missing ramin init, does it brake other hw?	Patrice Mandin

2007-11-14	Add new shared header file drm_internal.h.	Kristian Høgsberg
	This header file is shared across linux and bsd, but is not installed for user space to access. It's the place to put prototypes and data types that aren't platform or chipset specific, but still internal to the drm.
2007-11-14	nouveau: adjust the size of the NV34 context. That fixes mobile PPC cards.	Stephane Marchesin

2007-11-13	Fix ttmtest.	Thomas Hellstrom

2007-11-14	nouveau: Also wait until CACHE1 gets emptied.	Ben Skeggs

2007-11-14	Revert "nouveau: stub superioctl"	Ben Skeggs
	This reverts commit 2370ded79b4176d76cda1ec5f495fd33c2d566ed. Err.. didn't mean for that to slip in :)
2007-11-14	Merge branch 'fifo-cleanup' into upstream-master	Ben Skeggs

2007-11-14	nouveau: Attempt to wait for channel idle before we destroy it.	Ben Skeggs

2007-11-14	nouveau: Use "new" NV40 USER control regs.	Ben Skeggs
	Probably entirely pointless, but a simple change in any case.
2007-11-14	nouveau: store user control reg offsets in channel struct	Ben Skeggs

2007-11-14	nouveau: funcs to determine active channel on PFIFO.	Ben Skeggs

2007-11-14	nouveau: stub superioctl	Ben Skeggs

2007-11-10	Make sure PLLs are enabled before writing pipe configuration regs	Jesse Barnes
	Fix from the X driver. Make sure the PLLs are enabled and not in VGA mode before writing PIPE(A\|B)CONF regs to avoid hangs or crashes.
2007-11-09	suspend() and resume() need kernel 2.6.22 or later	Patrice Mandin

2007-11-09	drm: check edid data, so we deal well with broken driver.	Jerome Glisse

2007-11-09	drm: split edid handling in get_edid & add_edid_mode	Jerome Glisse
	This way driver can get_edid in output status detection (using all workaround which are in get_edid) and then provide this edid data in get_mode callback of output.
2007-11-09	i915: cleanup pageflip derefs sarea even if no sarea exists	Dave Airlie

2007-11-07	Merge branch 'master' of git+ssh://git.freedesktop.org/git/mesa/drm into ↵	Thomas Hellstrom
	modesetting-101 Conflicts: shared-core/i915_dma.c
2007-11-07	Don't overwrite TTM page flags.	Thomas Hellstrom

2007-11-07	i915: oops disable TTM is backwards	Dave Airlie

2007-11-06	Merge branch 'master' of git+ssh://git.freedesktop.org/git/mesa/drm into ↵	Thomas Hellstrom
	modesetting-101 Conflicts: linux-core/Makefile.kernel shared-core/i915_dma.c shared-core/i915_drv.h shared-core/i915_irq.c
2007-11-06	Avoid buffers not ending up on a list in some cases.	Thomas Hellstrom

2007-11-06	Add missing drm_regman.c file.	Thomas Hellstrom

2007-11-06	i915: disable TTM on 8xx chips for now until flushing is solved	Dave Airlie

2007-11-06	i915: compat code doesn't work in i8xx hw.	Dave Airlie

2007-11-06	[PATCH] i915: fix missing G33 detect in IS_I9XX	Zhenyu Wang
	G33 detect seems missing with Jesse's suspend/resume patch.

/************************************************************************** * * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * **************************************************************************/ /* Originally a fake version of the buffer manager so that we can * prototype the changes in a driver fairly quickly, has been fleshed * out to a fully functional interim solution. * * Basically wraps the old style memory management in the new * programming interface, but is more expressive and avoids many of * the bugs in the old texture manager. */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include <stdlib.h> #include <string.h> #include <assert.h> #include <errno.h> #include <xf86drm.h> #include <pthread.h> #include "intel_bufmgr.h" #include "intel_bufmgr_priv.h" #include "drm.h" #include "i915_drm.h" #include "mm.h" #include "libdrm_lists.h" #define ALIGN(value, alignment) ((value + alignment - 1) & ~(alignment - 1)) #define DBG(...) do { \ if (bufmgr_fake->bufmgr.debug) \ drmMsg(__VA_ARGS__); \ } while (0) /* Internal flags: */ #define BM_NO_BACKING_STORE 0x00000001 #define BM_NO_FENCE_SUBDATA 0x00000002 #define BM_PINNED 0x00000004 /* Wrapper around mm.c's mem_block, which understands that you must * wait for fences to expire before memory can be freed. This is * specific to our use of memcpy for uploads - an upload that was * processed through the command queue wouldn't need to care about * fences. */ #define MAX_RELOCS 4096 struct fake_buffer_reloc { /** Buffer object that the relocation points at. */ dri_bo *target_buf; /** Offset of the relocation entry within reloc_buf. */ uint32_t offset; /** Cached value of the offset when we last performed this relocation. */ uint32_t last_target_offset; /** Value added to target_buf's offset to get the relocation entry. */ uint32_t delta; /** Cache domains the target buffer is read into. */ uint32_t read_domains; /** Cache domain the target buffer will have dirty cachelines in. */ uint32_t write_domain; }; struct block { struct block *next, *prev; struct mem_block *mem; /* BM_MEM_AGP */ /** * Marks that the block is currently in the aperture and has yet to be * fenced. */ unsigned on_hardware:1; /** * Marks that the block is currently fenced (being used by rendering) and * can't be freed until @fence is passed. */ unsigned fenced:1; /** Fence cookie for the block. */ unsigned fence; /* Split to read_fence, write_fence */ dri_bo *bo; void *virtual; }; typedef struct _bufmgr_fake { dri_bufmgr bufmgr; pthread_mutex_t lock; unsigned long low_offset; unsigned long size; void *virtual; struct mem_block *heap; unsigned buf_nr; /* for generating ids */ /** * List of blocks which are currently in the GART but haven't been * fenced yet. */ struct block on_hardware; /** * List of blocks which are in the GART and have an active fence on them. */ struct block fenced; /** * List of blocks which have an expired fence and are ready to be evicted. */ struct block lru; unsigned int last_fence; unsigned fail:1; unsigned need_fence:1; int thrashing; /** * Driver callback to emit a fence, returning the cookie. * * This allows the driver to hook in a replacement for the DRM usage in * bufmgr_fake. * * Currently, this also requires that a write flush be emitted before * emitting the fence, but this should change. */ unsigned int (*fence_emit)(void *private); /** Driver callback to wait for a fence cookie to have passed. */ void (*fence_wait)(unsigned int fence, void *private); void *fence_priv; /** * Driver callback to execute a buffer. * * This allows the driver to hook in a replacement for the DRM usage in * bufmgr_fake. */ int (*exec)(dri_bo *bo, unsigned int used, void *priv); void *exec_priv; /** Driver-supplied argument to driver callbacks */ void *driver_priv; /* Pointer to kernel-updated sarea data for the last completed user irq */ volatile int *last_dispatch; int fd; int debug; int performed_rendering; } dri_bufmgr_fake; typedef struct _dri_bo_fake { dri_bo bo; unsigned id; /* debug only */ const char *name; unsigned dirty:1; /** has the card written to this buffer - we make need to copy it back */ unsigned card_dirty:1; unsigned int refcount; /* Flags may consist of any of the DRM_BO flags, plus * DRM_BO_NO_BACKING_STORE and BM_NO_FENCE_SUBDATA, which are the first two * driver private flags. */ uint64_t flags; /** Cache domains the target buffer is read into. */ uint32_t read_domains; /** Cache domain the target buffer will have dirty cachelines in. */ uint32_t write_domain; unsigned int alignment; int is_static, validated; unsigned int map_count; /** relocation list */ struct fake_buffer_reloc *relocs; int nr_relocs; /** * Total size of the target_bos of this buffer. * * Used for estimation in check_aperture. */ unsigned int child_size; struct block *block; void *backing_store; void (*invalidate_cb)(dri_bo *bo, void *ptr); void *invalidate_ptr; } dri_bo_fake; static int clear_fenced(dri_bufmgr_fake *bufmgr_fake, unsigned int fence_cookie); #define MAXFENCE 0x7fffffff static int FENCE_LTE( unsigned a, unsigned b ) { if (a == b) return 1; if (a < b && b - a < (1<<24)) return 1; if (a > b && MAXFENCE - a + b < (1<<24)) return 1; return 0; } void intel_bufmgr_fake_set_fence_callback(dri_bufmgr *bufmgr, unsigned int (*emit)(void *priv), void (*wait)(unsigned int fence, void *priv), void *priv) { dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bufmgr; bufmgr_fake->fence_emit = emit; bufmgr_fake->fence_wait = wait; bufmgr_fake->fence_priv = priv; } static unsigned int _fence_emit_internal(dri_bufmgr_fake *bufmgr_fake) { struct drm_i915_irq_emit ie; int ret, seq = 1; if (bufmgr_fake->fence_emit != NULL) return bufmgr_fake->fence_emit(bufmgr_fake->fence_priv); ie.irq_seq = &seq; ret = drmCommandWriteRead(bufmgr_fake->fd, DRM_I915_IRQ_EMIT, &ie, sizeof(ie)); if (ret) { drmMsg("%s: drm_i915_irq_emit: %d\n", __FUNCTION__, ret); abort(); } DBG("emit 0x%08x\n", seq); bufmgr_fake->last_fence = seq; return bufmgr_fake->last_fence; } static void _fence_wait_internal(dri_bufmgr_fake *bufmgr_fake, int seq) { struct drm_i915_irq_wait iw; int hw_seq, busy_count = 0; int ret; int kernel_lied; if (bufmgr_fake->fence_wait != NULL) { bufmgr_fake->fence_wait(seq, bufmgr_fake->fence_priv); return; } DBG("wait 0x%08x\n", iw.irq_seq); iw.irq_seq = seq; /* The kernel IRQ_WAIT implementation is all sorts of broken. * 1) It returns 1 to 0x7fffffff instead of using the full 32-bit unsigned * range. * 2) It returns 0 if hw_seq >= seq, not seq - hw_seq < 0 on the 32-bit * signed range. * 3) It waits if seq < hw_seq, not seq - hw_seq > 0 on the 32-bit * signed range. * 4) It returns -EBUSY in 3 seconds even if the hardware is still * successfully chewing through buffers. * * Assume that in userland we treat sequence numbers as ints, which makes * some of the comparisons convenient, since the sequence numbers are * all postive signed integers. * * From this we get several cases we need to handle. Here's a timeline. * 0x2 0x7 0x7ffffff8 0x7ffffffd * | | | | * ------------------------------------------------------------------- * * A) Normal wait for hw to catch up * hw_seq seq * | | * ------------------------------------------------------------------- * seq - hw_seq = 5. If we call IRQ_WAIT, it will wait for hw to catch up. * * B) Normal wait for a sequence number that's already passed. * seq hw_seq * | | * ------------------------------------------------------------------- * seq - hw_seq = -5. If we call IRQ_WAIT, it returns 0 quickly. * * C) Hardware has already wrapped around ahead of us * hw_seq seq * | | * ------------------------------------------------------------------- * seq - hw_seq = 0x80000000 - 5. If we called IRQ_WAIT, it would wait * for hw_seq >= seq, which may never occur. Thus, we want to catch this * in userland and return 0. * * D) We've wrapped around ahead of the hardware. * seq hw_seq * | | * ------------------------------------------------------------------- * seq - hw_seq = -(0x80000000 - 5). If we called IRQ_WAIT, it would return * 0 quickly because hw_seq >= seq, even though the hardware isn't caught up. * Thus, we need to catch this early return in userland and bother the * kernel until the hardware really does catch up. * * E) Hardware might wrap after we test in userland. * hw_seq seq * | | * ------------------------------------------------------------------- * seq - hw_seq = 5. If we call IRQ_WAIT, it will likely see seq >= hw_seq * and wait. However, suppose hw_seq wraps before we make it into the * kernel. The kernel sees hw_seq >= seq and waits for 3 seconds then * returns -EBUSY. This is case C). We should catch this and then return * successfully. * * F) Hardware might take a long time on a buffer. * hw_seq seq * | | * ------------------------------------------------------------------- * seq - hw_seq = 5. If we call IRQ_WAIT, if sequence 2 through 5 take too * long, it will return -EBUSY. Batchbuffers in the gltestperf demo were * seen to take up to 7 seconds. We should catch early -EBUSY return * and keep trying. */ do { /* Keep a copy of last_dispatch so that if the wait -EBUSYs because the * hardware didn't catch up in 3 seconds, we can see if it at least made * progress and retry. */ hw_seq = *bufmgr_fake->last_dispatch; /* Catch case C */ if (seq - hw_seq > 0x40000000) return; ret = drmCommandWrite(bufmgr_fake->fd, DRM_I915_IRQ_WAIT, &iw, sizeof(iw)); /* Catch case D */ kernel_lied = (ret == 0) && (seq - *bufmgr_fake->last_dispatch < -0x40000000); /* Catch case E */ if (ret == -EBUSY && (seq - *bufmgr_fake->last_dispatch > 0x40000000)) ret = 0; /* Catch case F: Allow up to 15 seconds chewing on one buffer. */ if ((ret == -EBUSY) && (hw_seq != *bufmgr_fake->last_dispatch)) busy_count = 0; else busy_count++; } while (kernel_lied || ret == -EAGAIN || ret == -EINTR || (ret == -EBUSY && busy_count < 5)); if (ret != 0) { drmMsg("%s:%d: Error waiting for fence: %s.\n", __FILE__, __LINE__, strerror(-ret)); abort(); } clear_fenced(bufmgr_fake, seq); } static int _fence_test(dri_bufmgr_fake *bufmgr_fake, unsigned fence) { /* Slight problem with wrap-around: */ return fence == 0 || FENCE_LTE(fence, bufmgr_fake->last_fence); } /** * Allocate a memory manager block for the buffer. */ static int alloc_block(dri_bo *bo) { dri_bo_fake *bo_fake = (dri_bo_fake *)bo; dri_bufmgr_fake *bufmgr_fake= (dri_bufmgr_fake *)bo->bufmgr; struct block *block = (struct block *)calloc(sizeof *block, 1); unsigned int align_log2 = ffs(bo_fake->alignment) - 1; unsigned int sz; if (!block) return 1; sz = (bo->size + bo_fake->alignment - 1) & ~(bo_fake->alignment - 1); block->mem = mmAllocMem(bufmgr_fake->heap, sz, align_log2, 0); if (!block->mem) { free(block); return 0; } DRMINITLISTHEAD(block); /* Insert at head or at tail??? */ DRMLISTADDTAIL(block, &bufmgr_fake->lru); block->virtual = (uint8_t *)bufmgr_fake->virtual + block->mem->ofs - bufmgr_fake->low_offset; block->bo = bo; bo_fake->block = block; return 1; } /* Release the card storage associated with buf: */ static void free_block(dri_bufmgr_fake *bufmgr_fake, struct block *block) { dri_bo_fake *bo_fake; DBG("free block %p %08x %d %d\n", block, block->mem->ofs, block->on_hardware, block->fenced); if (!block) return; bo_fake = (dri_bo_fake *)block->bo; if (!(bo_fake->flags & BM_NO_BACKING_STORE) && (bo_fake->card_dirty == 1)) { memcpy(bo_fake->backing_store, block->virtual, block->bo->size); bo_fake->card_dirty = 1; bo_fake->dirty = 1; } if (block->on_hardware) { block->bo = NULL; } else if (block->fenced) { block->bo = NULL; } else { DBG(" - free immediately\n"); DRMLISTDEL(block); mmFreeMem(block->mem); free(block); } } static void alloc_backing_store(dri_bo *bo) { dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr; dri_bo_fake *bo_fake = (dri_bo_fake *)bo; assert(!bo_fake->backing_store); assert(!(bo_fake->flags & (BM_PINNED|BM_NO_BACKING_STORE))); bo_fake->backing_store = malloc(bo->size); DBG("alloc_backing - buf %d %p %d\n", bo_fake->id, bo_fake->backing_store, bo->size); assert(bo_fake->backing_store); } static void free_backing_store(dri_bo *bo) { dri_bo_fake *bo_fake = (dri_bo_fake *)bo; if (bo_fake->backing_store) { assert(!(bo_fake->flags & (BM_PINNED|BM_NO_BACKING_STORE))); free(bo_fake->backing_store); bo_fake->backing_store = NULL; } } static void set_dirty(dri_bo *bo) { dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr; dri_bo_fake *bo_fake = (dri_bo_fake *)bo; if (bo_fake->flags & BM_NO_BACKING_STORE && bo_fake->invalidate_cb != NULL) bo_fake->invalidate_cb(bo, bo_fake->invalidate_ptr); assert(!(bo_fake->flags & BM_PINNED)); DBG("set_dirty - buf %d\n", bo_fake->id); bo_fake->dirty = 1; } static int evict_lru(dri_bufmgr_fake *bufmgr_fake, unsigned int max_fence) { struct block *block, *tmp; DBG("%s\n", __FUNCTION__); DRMLISTFOREACHSAFE(block, tmp, &bufmgr_fake->lru) { dri_bo_fake *bo_fake = (dri_bo_fake *)block->bo; if (bo_fake != NULL && (bo_fake->flags & BM_NO_FENCE_SUBDATA)) continue; if (block->fence && max_fence && !FENCE_LTE(block->fence, max_fence)) return 0; set_dirty(&bo_fake->bo); bo_fake->block = NULL; free_block(bufmgr_fake, block); return 1; } return 0; } static int evict_mru(dri_bufmgr_fake *bufmgr_fake) { struct block *block, *tmp; DBG("%s\n", __FUNCTION__); DRMLISTFOREACHSAFEREVERSE(block, tmp, &bufmgr_fake->lru) { dri_bo_fake *bo_fake = (dri_bo_fake *)block->bo; if (bo_fake && (bo_fake->flags & BM_NO_FENCE_SUBDATA)) continue; set_dirty(&bo_fake->bo); bo_fake->block = NULL; free_block(bufmgr_fake, block); return 1; } return 0; } /** * Removes all objects from the fenced list older than the given fence. */ static int clear_fenced(dri_bufmgr_fake *bufmgr_fake, unsigned int fence_cookie) { struct block *block, *tmp; int ret = 0;