Age | Commit message (Collapse) | Author |
|
|
|
|
|
Fix from the X driver. Make sure the PLLs are enabled and not in VGA mode
before writing PIPE(A|B)CONF regs to avoid hangs or crashes.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
G33 detect seems missing with Jesse's suspend/resume patch.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
The size passing to memset is wrong.
Signed-off-by: Li Zefan <lizf@cn.fujitsu.com>
|
|
|
|
Kernel "cleanfile" script run.
|
|
|
|
This patch is originally from malc0_, but since it used some NV40_*
regs, I edited them into hex values with a comment.
This seems to correspond quite well with my own mmio-trace,
for the parts I cared to check.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
radeon code.
|
|
|
|
Time out properly in the presence of signals.
|
|
This code relied on the CPU and GPU address for the aperture being the same,
On some r5xx hardware I was playing with I noticed that this isn't always true.
I wonder if this will fix some of those r4xx DRI issues we've seen in the past.
|
|
|
|
|
|
|
|
|
|
This mapping allows cached objects to be mapped in/out of the TT space
with the appropriate flushing calls.
It should put back the old CACHED functionality for snooped mappings
|
|
|
|
|
|
|
|
|