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This is the create (may want location flags), pread/pwrite/mmap
(performance tuning hints), and set_domain (will 32 bits be enough for
everyone?) ioctls. Left in the generic set are just flink/open/close.
The 2D driver must be updated for this change, and API but not ABI is broken
for 3D. The driver version is bumped to mark this.
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They are not unnecessary since the kernel's the only thing touching the ring.
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This requires that the X Server use the execbuf interface for buffer
submission, as it no longer has direct access to the ring. This is
therefore a flag day for the gem interface.
This also adds enter/leavevt ioctls for use by the X Server. These would
get stubbed out in a modesetting implementation, but are required while
in an environment where the device's state is only managed by the DRM while
X has the VT.
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The driver can know what hardware requires MI_BATCH_BUFFER vs
MI_BATCH_BUFFER_START; there's no reason to let user mode configure this.
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Without the user IRQ running constantly, there's no wakeup when the ring
empties to go retire requests and free buffers. Use a 1 second timer to make
that happen more often.
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This goes with the other hardware status page patch.
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Instead of throttling and execbuffer time, have the application ask to
throttle explicitly. This allows the throttle to happen less often, and
without holding the DRM lock.
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Place the buffer reuse links right into the dri_bo_gem object.
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The code was discarding the dri_bo_gem structure and saving only the kernel
handle. This lost the mmap address, causing pain when the next buffer user
wanted to map the buffer.
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I couldn't get the re-allocated HWS to work on my 965GM, so I just gave up
and made it persist across the lifetime of the driver instead.
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This will be used by the X Server for VT switch.
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struct_mutex cannot be held while blocking on DRM lock.
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Just renaming this function and related parameters to match terminology used
elsewhere in the driver.
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set_domain can block waiting for rendering to complete. If that process is
interrupted by a signal, it can return -EINTR. Catch this error in all
callers and correctly deal with the result.
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Conflicts:
linux-core/Makefile.kernel
shared-core/i915_drv.h
shared-core/nouveau_state.c
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The problem was revealed where on 965, the display list vertex buffer would see:
create -> (CPU, CPU)
set_domain (CPU, CPU) -> (CPU, CPU)
set_comain (CPU, 0) -> (CPU, 0) (no clflush occurred)
execbuf (GPU, 0) -> (CPU+GPU, 0) (still no clflush)
instead of:
create -> (CPU, CPU)
set_domain (CPU, CPU) -> (CPU, CPU)
set_comain (CPU, 0) -> (CPU, CPU)
execbuf (GPU, 0) -> (CPU+GPU, 0) (clflushed)
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Otherwise, 965 constant state buffers get re-relocated every exec. Ouch.
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Also remove an unreachable unlock.
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The i915 driver now works again.
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Object domain transfer can involve adding flush ops to the request queue,
and so the DRM lock must be held to avoid having the X server smash pointers
badly.
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The interrupt enable register cannot be used to temporarily disable
interrupts, instead use the interrupt mask register.
Note that this change means that a pile of buffers will be left stuck on the
chip as the final interrupts will not be recognized to come and drain things.
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This new ioctl returns whether re-using the buffer would force a wait.
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i915_gem_flush_pwrite optimizes short writes to the buffer by clflushing
only the modified pages, but it was miscomputing the number of pages.
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When reading from multiple domains, allow each cache to continue
to hold data until writes occur somewhere. This is done by
first leaving the read_domains alone at bind time (presumably the CPU read
cache contains valid data still) and then in set_domain, if no write_domain
is specified, the new read domains are simply merged into the existing read
domains.
A huge comment was added above set_domain to explain how things are
expected to work.
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Newly allocated objects need to be in the CPU domain as they've just been
cleared by the CPU. Also, unmapping objects from the GTT needs to put them
into the CPU domain, both to flush rendering as well as to ensure that any
paging action gets flushed before we remap to the GTT.
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Commands in the ring are parsed and started when the head pointer passes by
them, but they are not necessarily finished until a MI_FLUSH happens. This
patch inserts a flush after the execbuffer (the only place a flush wasn't
already happening).
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Recording the tail pointer in a local variable improves performance, but if
someone messes up and fails to reload at the right time, the driver will
write commands to the wrong part of the ring and scramble execution badly.
This change (available by setting I915_RING_VALIDATE to 1) checks to make
sure the cached tail pointer matches the hardware tail pointer at each ring
buffer addition, calling BUG_ON when that's not true.
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