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At DDX commit Chris mentioned the tendency we have of finding out more
PCI IDs only when users report. So Let's add all new reserved Haswell IDs.
Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
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When publishing first HSW ids we weren't allowed to use "GT3" codname.
But this is the correct codname and Mesa is using it already.
So to avoid people getting confused why in Mesa it is called GT3 and here
it is called GT2_PLUS let's fix this name in a standard and correct way.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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Render the crosshairs for 565 and x888/a888 formats.
v2: Use the drm format to determine cairo format
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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When adding the name tracking, I missed removing from the name table
when the bo was deleted, leaving a dangling pointer.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
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Things are worse if we issueibcmds with bogus gpu ptrs, so it is better
to just make userspace crash when things go pear shaped.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
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Due to the evil userspace buffer tracking we have to do, and hacks for
creating GEM buffer from fbdev/scanout, "evil-twin" fd_bo objects are
problematic. So introduce hashtable tracking of bo's and dev's, to
avoid getting duplicate fd_bo ptrs for the same underlying gem object,
in particular when importing via flink name.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
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Signed-off-by: Marek Olšák <maraeo@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Now that this driver is merged add the header file.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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v2: Fix the test for has_vebox
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
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Super-cheezy way to synchronization between mesa and ddx.. the
SET_ACTIVE ioctl gives us a way to stash a 32b # w/ a GEM bo, and
GET_BUFINFO gives us a way to retrieve it. We use this to stash
the timestamp of the last ISSUEIBCMDS on the buffer.
To avoid an obscene amount of syscalls, we:
1) Only set the timestamp for buffers w/ an flink name, ie.
only buffers shared across processes. This is enough to
catch the DRI2 buffers.
2) Only set the timestamp for buffers submitted to the 3d ring
and only check the timestamps on buffers submitted to the
2d ring. This should be enough to handle synchronizing of
presentation blit. We could do synchronization in the other
direction too, but that would be problematic if we are using
the 3d ring from DDX, since client side wouldn't know this.
The waiting on timestamp happens before flush, and setting of
timestamp happens after flush. It is transparent to the user
of libdrm_freedreno as all the tracking of buffers happens via
_emit_reloc()..
Signed-off-by: Rob Clark <robclark@freedesktop.org>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Signed-off-by: Rob Clark <robclark@freedesktop.org>
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Gallium driver will need to query this to figure out whether to load the
a2xx or a3xx driver.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
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YUV420 support is trivial to add since the code already supports
YVU420.
But it looks like the YVU420 support is a bit broken. The chroma
planes are passed in the wrong order to the fill functions, so
fix that while were at it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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The fourcc is inside the format_info structure, so if we want to use
it inside the various fill_tiles functions, we need to pass down the
whole format_info, not just the rgb/yuv infos.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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Spelling out eDP or DP make for a ridicilously long string which plays
havoc with formatting. Just say eDP or DP.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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libkms only has the xrgb8888 format, so we're overallocating the bo by
quite a lot in some cases. But we still need to get the pitch from the
libkms since it's the driver that decides how to align it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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The function returns returns 0 on success or a negative value in case of an
error, except when given invalid attributes in which case it returns the
positive EINVAL value. Replace that with -EINVAL to allow the caller to detect
errors with a < 0 check.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Jakob Bornecrantz <wallbraker@gmail.com>
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Wrap the header in extern "C" { ... };.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Jakob Bornecrantz <wallbraker@gmail.com>
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Needed for RB_COPY_DEST_BASE register on a3xx.
Signed-off-by: Rob Clark <robdclark@gmail.com>
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v2: Only writte tile index if flags for it is set
v3: Remove useless allow2d scanout flags
v4: Split radeon_drm.h update to its own patch
v5: update against lastest next tree for radeon
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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v2: sync with radeon-next tree for 3.10
http://cgit.freedesktop.org/~agd5f/linux/log/?h=drm-next-3.10-wip
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
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It accidentally used the cmd id for the gen7 command and had an
outdated lenght field. Spotted while trying to make sense of an ivb
error_state from mesa 7.11 ...
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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The second digit was off by one, which meant we accidentally treated
GT(n) as GT(n-1). This also meant no support for GT1 at all.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
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If clock_gettime did fail, it would return -1 and set errno.
What we really want to strerror() is the errno.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
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I even compile time tested this on a panda with make dist!
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
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it's not even shipped in the tarball.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
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Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
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Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Protect the macro argument evaluations with parens.
This is already touching most lines, so while at it, fix up all white
space to uniform style throughout the file.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Currently single pushbuffer can take up to 80% of VRAM and 80% of GART.
As this value seems to be arbitrary (and user may need to set it differently)
this patch adds support for 2 environment variables:
NOUVEAU_LIBDRM_VRAM_LIMIT_PERCENT (default 80)
NOUVEAU_LIBDRM_GART_LIMIT_PERCENT (default 80)
which will let users override pushbuffer VRAM/GART limits.
Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com>
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Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com>
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fix error in previous patch
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.com>
Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
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Install test programs is useful in cross compilation case. By default
the behavior is the same and test programs aren't installed in $bindir.
If --enable-install-test-programs is set then test programs are
installed in $bindir.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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This patch adds library and test application for g2d gpu(fimg2d).
The fimg2d hardware is a 2D graphics accelerator(G2D) that
supports Bit Block Transfer(BitBLT).
The library includes the following primitive drawing operations:
.solid fill - This operation fills the given buffer with
the given color data.
.copy - This operation copies contents in source buffer to
destination buffer.
.copy_with_scale - This operation copies contents in source buffer
to destination buffer scaling up or down properly.
.blend - This operation blends contents in source buffer with
the ones in destination buffer.
And the above operations uses gem handle or user space address
allocated by malloc() as source or destination buffer.
And the test application includes just simple primitive drawing
tests with the above library.
And the guide to test is as the following,
"#exynos_fimg2d_test -s connector_id@crtc_id:mode"
With this above simple command, four primitive drawing operations
would be called step by step and also rendered on the output device
to the given connector and crtc id.
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Rob Clark <robdclark@gmail.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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The libdrm_freedreno helper layer for use by xf86-video-freedreno,
fdre (freedreno r/e library and tests for driving gpu), and eventual
gallium driver for the Adreno GPU. This uses the msm gpu driver
from QCOM's android kernel tree.
Note that current msm kernel driver is a bit strange. It provides a
DRM interface for GEM, which is basically sufficient to have DRI2
working. But it does not provide KMS. And interface to 2d and 3d
cores is via different other devices (/dev/kgsl-*). This is not
quite how I'd write a DRM driver, but at this stage it is useful for
xf86-video-freedreno and fdre (and eventual gallium driver) to be
able to work on existing kernel driver from QCOM, to allow to
capture cmdstream dumps from the binary blob drivers without having
to reboot. So libdrm_freedreno attempts to hide most of the crazy.
The intention is that when there is a proper kernel driver, it will
be mostly just changes in libdrm_freedreno to adapt the gallium
driver and xf86-video-freedreno (ignoring the fbdev->KMS changes).
So don't look at freedreno as an example of how to write a libdrm
module or a DRM driver.. it is just an attempt to paper over a non-
standard kernel driver architecture.
v1: original
v2: hold ref's to pending bo's (because qcom's kernel driver doesn't),
various bug fixes, add ringbuffer markers so we can emit IB's to
portion of ringbuffer (so that gallium driver can use a single
ringbuffer for both tile cmds and draw cmds.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
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Intel GPU Tools is newer and arguably better. This change doesn't
completely merge the files because it's a bit simpler if we move the
I9XX macro over to Intel GPU Tools, and don't move over a few macros
from IGT that libdrm doesn't care about.
It has been discussed, and would seem even easier if Intel GPU Tools
simply used the libdrm header files. Whether or not we move to that,
this should help that effort.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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On Gen6, bit 15 is now `Depth Clear Value Valid`. This was being treated
as part of the length, and failing the rest of the batchbuffer decode.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
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We didn't set the ring flag for BLT batches, so they got run on the
render ring. Shenanigans ensued, especially when we sent commands that
were only valid on the BLT ring.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
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I'm fairly sure the extra flags it specifies no longer exist, so
there is no point in keeping it. It only adds a warning when
running make distcheck.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
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