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- fix offset for nv04
- use it in nv10 graph ctx switch for getting next channel
- dump NV10_PGRAPH_TRAPPED_DATA_HIGH on nv10+
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- add forgotten init value
- use the same PGRAPH_DEBUG than the blob
- remove init of ddx reg : it should be done with object
- better handle of channel destruction
hope I didn't break anything ;)
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Seems we already have a nv4c_ctx_init() somehow, a quick check shows the
ucode matches it still.
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of cards.
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Microcode is similar enough to the NV4A one that it should be able to use
the same initial PGRAPH context. One day this mess will go away, honest..
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Makes 0x2220 work the same way as on NV40.
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With the previous linux commit, an AGP aperture at the end of the address space
would have wrapped to 0 and the test would have failed.
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The brief descriptions usually had the wrong filename in them.
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Ensure NV_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLE gets set, otherwise channels
will appear to "freeze" in some circumstances.
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The i830 and newer intel 2D code adds the AGP base to map offsets already,
because it wasn't doing the AGP enable which used to set dev->agp->base.
Credit goes to Zhenyu for finding the issue.
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Also, annotate where signs change, to hopefully remind the reader of these
issues in the future.
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This should improve multi fifo
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Fixes #11868
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We really should be providing static values like the nv40 PGRAPH code does,
however, this will do for now to keep X at least working.
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All interrupts are still masked by PMC until init is finished.
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init after irq_postinstall)
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Not all drivers call enable (intel), but they would still like to use this
member in driver code.
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