summaryrefslogtreecommitdiff
path: root/shared
diff options
context:
space:
mode:
Diffstat (limited to 'shared')
-rw-r--r--shared/mga_drv.h36
-rw-r--r--shared/r128_cce.c1
-rw-r--r--shared/r128_drv.h34
-rw-r--r--shared/radeon_cp.c7
-rw-r--r--shared/radeon_drm.h2
-rw-r--r--shared/radeon_drv.h38
6 files changed, 56 insertions, 62 deletions
diff --git a/shared/mga_drv.h b/shared/mga_drv.h
index a5085b06..0e650b42 100644
--- a/shared/mga_drv.h
+++ b/shared/mga_drv.h
@@ -90,14 +90,14 @@ typedef struct drm_mga_private {
unsigned int texture_offset;
unsigned int texture_size;
- drm_map_t *sarea;
- drm_map_t *fb;
- drm_map_t *mmio;
- drm_map_t *status;
- drm_map_t *warp;
- drm_map_t *primary;
- drm_map_t *buffers;
- drm_map_t *agp_textures;
+ drm_local_map_t *sarea;
+ drm_local_map_t *fb;
+ drm_local_map_t *mmio;
+ drm_local_map_t *status;
+ drm_local_map_t *warp;
+ drm_local_map_t *primary;
+ drm_local_map_t *buffers;
+ drm_local_map_t *agp_textures;
} drm_mga_private_t;
/* mga_dma.c */
@@ -131,32 +131,30 @@ extern int mga_getparam( DRM_IOCTL_ARGS );
extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv );
extern int mga_warp_init( drm_mga_private_t *dev_priv );
-#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER()
-
+#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER(dev_priv->primary)
+#if defined(__linux__) && defined(__alpha__)
#define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle))
#define MGA_ADDR( reg ) (MGA_BASE(reg) + reg)
#define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg )
#define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg )
-#ifdef __alpha__
#define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg)))
#define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg)))
-#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0)
-#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0)
+#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(dev_priv->mmio); MGA_DEREF( reg ) = val; } while (0)
+#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(dev_priv->mmio); MGA_DEREF8( reg ) = val; } while (0)
static inline u32 _MGA_READ(u32 *addr)
{
- DRM_READMEMORYBARRIER();
+ DRM_READMEMORYBARRIER(dev_priv->mmio);
return *(volatile u32 *)addr;
}
-
#else
-#define MGA_READ( reg ) MGA_DEREF( reg )
-#define MGA_READ8( reg ) MGA_DEREF8( reg )
-#define MGA_WRITE( reg, val ) do { MGA_DEREF( reg ) = val; } while (0)
-#define MGA_WRITE8( reg, val ) do { MGA_DEREF8( reg ) = val; } while (0)
+#define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg))
+#define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg))
+#define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val))
+#define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val))
#endif
#define DWGREG0 0x1c00
diff --git a/shared/r128_cce.c b/shared/r128_cce.c
index 5175885e..8d305b75 100644
--- a/shared/r128_cce.c
+++ b/shared/r128_cce.c
@@ -579,6 +579,7 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
(dev_priv->ring.size / sizeof(u32)) - 1;
dev_priv->ring.high_mark = 128;
+ dev_priv->ring.ring_rptr = dev_priv->ring_rptr;
dev_priv->sarea_priv->last_frame = 0;
R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame );
diff --git a/shared/r128_drv.h b/shared/r128_drv.h
index 763fcb3a..5e6f1215 100644
--- a/shared/r128_drv.h
+++ b/shared/r128_drv.h
@@ -34,8 +34,8 @@
#ifndef __R128_DRV_H__
#define __R128_DRV_H__
-#define GET_RING_HEAD(ring) DRM_READ32( (volatile u32 *) (ring)->head )
-#define SET_RING_HEAD(ring,val) DRM_WRITE32( (volatile u32 *) (ring)->head, (val) )
+#define GET_RING_HEAD(ring) DRM_READ32( (ring)->ring_rptr, 0 ) /* (ring)->head */
+#define SET_RING_HEAD(ring,val) DRM_WRITE32( (ring)->ring_rptr, 0, (val) ) /* (ring)->head */
typedef struct drm_r128_freelist {
unsigned int age;
@@ -56,6 +56,7 @@ typedef struct drm_r128_ring_buffer {
int space;
int high_mark;
+ drm_local_map_t *ring_rptr;
} drm_r128_ring_buffer_t;
typedef struct drm_r128_private {
@@ -98,13 +99,13 @@ typedef struct drm_r128_private {
u32 depth_pitch_offset_c;
u32 span_pitch_offset_c;
- drm_map_t *sarea;
- drm_map_t *fb;
- drm_map_t *mmio;
- drm_map_t *cce_ring;
- drm_map_t *ring_rptr;
- drm_map_t *buffers;
- drm_map_t *agp_textures;
+ drm_local_map_t *sarea;
+ drm_local_map_t *fb;
+ drm_local_map_t *mmio;
+ drm_local_map_t *cce_ring;
+ drm_local_map_t *ring_rptr;
+ drm_local_map_t *buffers;
+ drm_local_map_t *agp_textures;
} drm_r128_private_t;
typedef struct drm_r128_buf_priv {
@@ -370,15 +371,10 @@ extern int r128_cce_indirect( DRM_IOCTL_ARGS );
#define R128_PERFORMANCE_BOXES 0
-
-#define R128_BASE(reg) ((unsigned long)(dev_priv->mmio->handle))
-#define R128_ADDR(reg) (R128_BASE( reg ) + reg)
-
-#define R128_READ(reg) DRM_READ32( (volatile u32 *) R128_ADDR(reg) )
-#define R128_WRITE(reg,val) DRM_WRITE32( (volatile u32 *) R128_ADDR(reg), (val) )
-
-#define R128_READ8(reg) DRM_READ8( (volatile u8 *) R128_ADDR(reg) )
-#define R128_WRITE8(reg,val) DRM_WRITE8( (volatile u8 *) R128_ADDR(reg), (val) )
+#define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
+#define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
+#define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
+#define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
#define R128_WRITE_PLL(addr,val) \
do { \
@@ -453,7 +449,7 @@ do { \
#if defined(__powerpc__)
#define r128_flush_write_combine() (void) GET_RING_HEAD( &dev_priv->ring )
#else
-#define r128_flush_write_combine() DRM_WRITEMEMORYBARRIER()
+#define r128_flush_write_combine() DRM_WRITEMEMORYBARRIER(dev_priv->ring_rptr)
#endif
diff --git a/shared/radeon_cp.c b/shared/radeon_cp.c
index 6994fe9e..89c9eab1 100644
--- a/shared/radeon_cp.c
+++ b/shared/radeon_cp.c
@@ -926,11 +926,11 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
/* Writeback doesn't seem to work everywhere, test it first */
- DRM_WRITE32( &dev_priv->scratch[1], 0 );
+ DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 );
RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef );
for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) {
- if ( DRM_READ32( &dev_priv->scratch[1] ) == 0xdeadbeef )
+ if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef )
break;
DRM_UDELAY( 1 );
}
@@ -1217,6 +1217,7 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
(dev_priv->ring.size / sizeof(u32)) - 1;
dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
+ dev_priv->ring.ring_rptr = dev_priv->ring_rptr;
#if __REALLY_HAVE_SG
if ( dev_priv->is_pci ) {
@@ -1542,7 +1543,7 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
drm_buf_t *buf;
int i, t;
int start;
- u32 done_age = DRM_READ32(&dev_priv->scratch[1]);
+ u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
if ( ++dev_priv->last_buf >= dma->buf_count )
dev_priv->last_buf = 0;
diff --git a/shared/radeon_drm.h b/shared/radeon_drm.h
index 512d36b9..3ab57309 100644
--- a/shared/radeon_drm.h
+++ b/shared/radeon_drm.h
@@ -396,7 +396,7 @@ typedef struct drm_radeon_init {
enum {
RADEON_INIT_CP = 0x01,
RADEON_CLEANUP_CP = 0x02,
- RADEON_INIT_R200_CP = 0x03,
+ RADEON_INIT_R200_CP = 0x03
} func;
unsigned long sarea_priv_offset;
int is_pci;
diff --git a/shared/radeon_drv.h b/shared/radeon_drv.h
index fb8fbafe..502ba89b 100644
--- a/shared/radeon_drv.h
+++ b/shared/radeon_drv.h
@@ -31,8 +31,8 @@
#ifndef __RADEON_DRV_H__
#define __RADEON_DRV_H__
-#define GET_RING_HEAD(ring) DRM_READ32( (volatile u32 *) (ring)->head )
-#define SET_RING_HEAD(ring,val) DRM_WRITE32( (volatile u32 *) (ring)->head , (val))
+#define GET_RING_HEAD(ring) DRM_READ32( (ring)->ring_rptr, 0 ) /* (ring)->head */
+#define SET_RING_HEAD(ring,val) DRM_WRITE32( (ring)->ring_rptr, 0, (val) ) /* (ring)->head */
typedef struct drm_radeon_freelist {
unsigned int age;
@@ -53,6 +53,7 @@ typedef struct drm_radeon_ring_buffer {
int space;
int high_mark;
+ drm_local_map_t *ring_rptr;
} drm_radeon_ring_buffer_t;
typedef struct drm_radeon_depth_clear_t {
@@ -126,13 +127,13 @@ typedef struct drm_radeon_private {
drm_radeon_depth_clear_t depth_clear;
- drm_map_t *sarea;
- drm_map_t *fb;
- drm_map_t *mmio;
- drm_map_t *cp_ring;
- drm_map_t *ring_rptr;
- drm_map_t *buffers;
- drm_map_t *agp_textures;
+ drm_local_map_t *sarea;
+ drm_local_map_t *fb;
+ drm_local_map_t *mmio;
+ drm_local_map_t *cp_ring;
+ drm_local_map_t *ring_rptr;
+ drm_local_map_t *buffers;
+ drm_local_map_t *agp_textures;
struct mem_block *agp_heap;
struct mem_block *fb_heap;
@@ -267,8 +268,10 @@ extern void radeon_do_release(drm_device_t *dev);
#define RADEON_SCRATCH_UMSK 0x0770
#define RADEON_SCRATCH_ADDR 0x0774
+#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
+
#define GET_SCRATCH( x ) (dev_priv->writeback_works \
- ? DRM_READ32( &dev_priv->scratch[(x)] ) \
+ ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
: RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
@@ -687,15 +690,10 @@ extern void radeon_do_release(drm_device_t *dev);
#define RADEON_RING_HIGH_MARK 128
-
-#define RADEON_BASE(reg) ((unsigned long)(dev_priv->mmio->handle))
-#define RADEON_ADDR(reg) (RADEON_BASE( reg ) + reg)
-
-#define RADEON_READ(reg) DRM_READ32( (volatile u32 *) RADEON_ADDR(reg) )
-#define RADEON_WRITE(reg,val) DRM_WRITE32( (volatile u32 *) RADEON_ADDR(reg), (val) )
-
-#define RADEON_READ8(reg) DRM_READ8( (volatile u8 *) RADEON_ADDR(reg) )
-#define RADEON_WRITE8(reg,val) DRM_WRITE8( (volatile u8 *) RADEON_ADDR(reg), (val) )
+#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
+#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
+#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
+#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
#define RADEON_WRITE_PLL( addr, val ) \
do { \
@@ -859,7 +857,7 @@ do { \
#define COMMIT_RING() do { \
/* Flush writes to ring */ \
- DRM_READMEMORYBARRIER(); \
+ DRM_READMEMORYBARRIER(dev_priv->mmio); \
GET_RING_HEAD( &dev_priv->ring ); \
RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
/* read from PCI bus to ensure correct posting */ \
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 12:26:05 +0000