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Diffstat (limited to 'shared/radeon_cp.c')
-rw-r--r--shared/radeon_cp.c63
1 files changed, 7 insertions, 56 deletions
diff --git a/shared/radeon_cp.c b/shared/radeon_cp.c
index 89c9eab1..b4d0e4b6 100644
--- a/shared/radeon_cp.c
+++ b/shared/radeon_cp.c
@@ -36,11 +36,6 @@
#define RADEON_FIFO_DEBUG 0
-#if defined(__alpha__) || defined(__powerpc__)
-# define PCIGART_ENABLED
-#else
-# undef PCIGART_ENABLED
-#endif
/* CP microcode (from ATI) */
@@ -885,6 +880,7 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
/* Set the write pointer delay */
RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
+ RADEON_READ( RADEON_CP_RB_WPTR_DELAY ); /* read back to propagate */
/* Initialize the ring buffer's read and write pointers */
cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
@@ -926,11 +922,11 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
/* Writeback doesn't seem to work everywhere, test it first */
- DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 );
+ DRM_WRITE32( &dev_priv->scratch[1], 0 );
RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef );
for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) {
- if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef )
+ if ( DRM_READ32( &dev_priv->scratch[1] ) == 0xdeadbeef )
break;
DRM_UDELAY( 1 );
}
@@ -990,17 +986,6 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
dev_priv->is_pci = init->is_pci;
-#if !defined(PCIGART_ENABLED)
- /* PCI support is not 100% working, so we disable it here.
- */
- if ( dev_priv->is_pci ) {
- DRM_ERROR( "PCI GART not yet supported for Radeon!\n" );
- dev->dev_private = (void *)dev_priv;
- radeon_do_cleanup_cp(dev);
- return DRM_ERR(EINVAL);
- }
-#endif
-
if ( dev_priv->is_pci && !dev->sg ) {
DRM_ERROR( "PCI GART memory not allocated!\n" );
dev->dev_private = (void *)dev_priv;
@@ -1217,7 +1202,6 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
(dev_priv->ring.size / sizeof(u32)) - 1;
dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
- dev_priv->ring.ring_rptr = dev_priv->ring_rptr;
#if __REALLY_HAVE_SG
if ( dev_priv->is_pci ) {
@@ -1355,9 +1339,6 @@ int radeon_cp_stop( DRM_IOCTL_ARGS )
DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t *)data, sizeof(stop) );
- if (!dev_priv->cp_running)
- return 0;
-
/* Flush any pending CP commands. This ensures any outstanding
* commands are exectuted by the engine before we turn it off.
*/
@@ -1385,39 +1366,6 @@ int radeon_cp_stop( DRM_IOCTL_ARGS )
return 0;
}
-
-void radeon_do_release( drm_device_t *dev )
-{
- drm_radeon_private_t *dev_priv = dev->dev_private;
- int ret;
-
- if (dev_priv) {
- if (dev_priv->cp_running) {
- /* Stop the cp */
- while ((ret = radeon_do_cp_idle( dev_priv )) != 0) {
- DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
-#ifdef __linux__
- schedule();
-#else
- tsleep(&ret, PZERO, "rdnrel", 1);
-#endif
- }
- radeon_do_cp_stop( dev_priv );
- radeon_do_engine_reset( dev );
- }
-
- /* Disable *all* interrupts */
- RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
-
- /* Free memory heap structures */
- radeon_mem_takedown( &(dev_priv->agp_heap) );
- radeon_mem_takedown( &(dev_priv->fb_heap) );
-
- /* deallocate kernel resources */
- radeon_do_cleanup_cp( dev );
- }
-}
-
/* Just reset the CP ring. Called as part of an X Server engine reset.
*/
int radeon_cp_reset( DRM_IOCTL_ARGS )
@@ -1449,6 +1397,9 @@ int radeon_cp_idle( DRM_IOCTL_ARGS )
LOCK_TEST_WITH_RETURN( dev );
+/* if (dev->irq) */
+/* radeon_emit_and_wait_irq( dev ); */
+
return radeon_do_cp_idle( dev_priv );
}
@@ -1543,7 +1494,7 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
drm_buf_t *buf;
int i, t;
int start;
- u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
+ u32 done_age = DRM_READ32(&dev_priv->scratch[1]);
if ( ++dev_priv->last_buf >= dma->buf_count )
dev_priv->last_buf = 0;