diff options
Diffstat (limited to 'shared-core')
| -rw-r--r-- | shared-core/drm.h | 102 | ||||
| -rw-r--r-- | shared-core/i915_drv.h | 17 |
2 files changed, 84 insertions, 35 deletions
diff --git a/shared-core/drm.h b/shared-core/drm.h index 0e3b9b89..6fccec39 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -697,9 +697,10 @@ typedef struct drm_fence_arg { } drm_fence_arg_t; /* Buffer permissions, referring to how the GPU uses the buffers. - these translate to fence types used for the buffers. - Typically a texture buffer is read, A destination buffer is write and - a command (batch-) buffer is exe. Can be or-ed together. */ + * these translate to fence types used for the buffers. + * Typically a texture buffer is read, A destination buffer is write and + * a command (batch-) buffer is exe. Can be or-ed together. + */ #define DRM_BO_FLAG_READ 0x00000001 #define DRM_BO_FLAG_WRITE 0x00000002 @@ -707,47 +708,82 @@ typedef struct drm_fence_arg { /* * Status flags. Can be read to determine the actual state of a buffer. + * Can also be set in the buffer mask before validation. */ -/* - * Cannot evict this buffer. Not even with force. This type of buffer should - * only be available for root, and must be manually removed before buffer - * manager shutdown or swapout. +/* + * Mask: Never evict this buffer. Not even with force. This type of buffer is only + * available to root and must be manually removed before buffer manager shutdown + * or lock. + * Flags: Acknowledge */ #define DRM_BO_FLAG_NO_EVICT 0x00000010 -/* Always keep a system memory shadow to a vram buffer */ -#define DRM_BO_FLAG_SHADOW_VRAM 0x00000020 -/* The buffer is shareable with other processes */ + +/* + * Mask: Require that the buffer is placed in mappable memory when validated. + * If not set the buffer may or may not be in mappable memory when validated. + * Flags: If set, the buffer is in mappable memory. + */ +#define DRM_BO_FLAG_MAPPABLE 0x00000020 + +/* Mask: The buffer should be shareable with other processes. + * Flags: The buffer is shareable with other processes. + */ #define DRM_BO_FLAG_SHAREABLE 0x00000040 -/* The buffer is currently cached */ + +/* Mask: If set, place the buffer in cache-coherent memory if available. + * If clear, never place the buffer in cache coherent memory if validated. + * Flags: The buffer is currently in cache-coherent memory. + */ #define DRM_BO_FLAG_CACHED 0x00000080 -/* Make sure that every time this buffer is validated, it ends up on the same - * location. The buffer will also not be evicted when claiming space for - * other buffers. Basically a pinned buffer but it may be thrown out as - * part of buffer manager shutdown or swapout. Not supported yet.*/ + +/* Mask: Make sure that every time this buffer is validated, + * it ends up on the same location provided that the memory mask is the same. + * The buffer will also not be evicted when claiming space for + * other buffers. Basically a pinned buffer but it may be thrown out as + * part of buffer manager shutdown or locking. + * Flags: Acknowledge. + */ #define DRM_BO_FLAG_NO_MOVE 0x00000100 -/* Make sure the buffer is in cached memory when mapped for reading */ -#define DRM_BO_FLAG_READ_CACHED 0x00080000 -/* When there is a choice between VRAM and TT, prefer VRAM. - The default behaviour is to prefer TT. */ -#define DRM_BO_FLAG_PREFER_VRAM 0x00040000 -/* Bind this buffer cached if the hardware supports it. */ -#define DRM_BO_FLAG_BIND_CACHED 0x0002000 +/* Mask: Make sure the buffer is in cached memory when mapped for reading. + * Flags: Acknowledge. + */ +#define DRM_BO_FLAG_READ_CACHED 0x00080000 -/* System Memory */ +/* Mask: Force DRM_BO_FLAG_CACHED flag strictly also if it is set. + * Flags: Acknowledge. + */ +#define DRM_BO_FLAG_FORCE_CACHING 0x00002000 + +/* + * Mask: Force DRM_BO_FLAG_MAPPABLE flag strictly also if it is clear. + * Flags: Acknowledge. + */ +#define DRM_BO_FLAG_FORCE_MAPPABLE 0x00004000 + +/* + * Memory type flags that can be or'ed together in the mask, but only + * one appears in flags. + */ + +/* System memory */ #define DRM_BO_FLAG_MEM_LOCAL 0x01000000 /* Translation table memory */ #define DRM_BO_FLAG_MEM_TT 0x02000000 /* Vram memory */ #define DRM_BO_FLAG_MEM_VRAM 0x04000000 -/* Unmappable Vram memory */ -#define DRM_BO_FLAG_MEM_VRAM_NM 0x08000000 +/* Up to the driver to define. */ +#define DRM_BO_FLAG_MEM_PRIV0 0x08000000 +#define DRM_BO_FLAG_MEM_PRIV1 0x10000000 +#define DRM_BO_FLAG_MEM_PRIV2 0x20000000 +#define DRM_BO_FLAG_MEM_PRIV3 0x40000000 +#define DRM_BO_FLAG_MEM_PRIV4 0x80000000 + /* Memory flag mask */ #define DRM_BO_MASK_MEM 0xFF000000 +#define DRM_BO_MASK_MEMTYPE 0xFF0000A0 -/* When creating a buffer, Avoid system storage even if allowed */ -#define DRM_BO_HINT_AVOID_LOCAL 0x00000001 /* Don't block on validate and map */ #define DRM_BO_HINT_DONT_BLOCK 0x00000002 /* Don't place this buffer on the unfenced list.*/ @@ -756,9 +792,6 @@ typedef struct drm_fence_arg { #define DRM_BO_HINT_ALLOW_UNFENCED_MAP 0x00000010 -/* Driver specific flags. Could be for example rendering engine */ -#define DRM_BO_MASK_DRIVER 0x00F00000 - typedef enum { drm_bo_type_dc, drm_bo_type_user, @@ -826,8 +859,13 @@ typedef struct drm_bo_arg{ #define DRM_BO_MEM_LOCAL 0 #define DRM_BO_MEM_TT 1 #define DRM_BO_MEM_VRAM 2 -#define DRM_BO_MEM_VRAM_NM 3 -#define DRM_BO_MEM_TYPES 2 /* For now. */ +#define DRM_BO_MEM_PRIV0 3 +#define DRM_BO_MEM_PRIV1 4 +#define DRM_BO_MEM_PRIV2 5 +#define DRM_BO_MEM_PRIV3 6 +#define DRM_BO_MEM_PRIV4 7 + +#define DRM_BO_MEM_TYPES 8 /* For now. */ typedef union drm_mm_init_arg{ struct { diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index 5a76cb15..34875db8 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -126,7 +126,9 @@ typedef struct drm_i915_private { uint32_t flush_pending; uint32_t saved_flush_status; #endif - +#ifdef I915_HAVE_BUFFER + void *agp_iomap; +#endif spinlock_t swaps_lock; drm_i915_vbl_swap_t vbl_swaps; unsigned int swaps_pending; @@ -183,10 +185,12 @@ extern void i915_mem_release(drm_device_t * dev, extern void i915_fence_handler(drm_device_t *dev); -extern int i915_fence_emit_sequence(drm_device_t *dev, uint32_t flags, +extern int i915_fence_emit_sequence(drm_device_t *dev, uint32_t class, + uint32_t flags, uint32_t *sequence, uint32_t *native_type); -extern void i915_poke_flush(drm_device_t *dev); +extern void i915_poke_flush(drm_device_t *dev, uint32_t class); +extern int i915_fence_has_irq(drm_device_t *dev, uint32_t class, uint32_t flags); #endif #ifdef I915_HAVE_BUFFER @@ -194,6 +198,12 @@ extern void i915_poke_flush(drm_device_t *dev); extern drm_ttm_backend_t *i915_create_ttm_backend_entry(drm_device_t *dev); extern int i915_fence_types(uint32_t buffer_flags, uint32_t *class, uint32_t *type); extern int i915_invalidate_caches(drm_device_t *dev, uint32_t buffer_flags); +extern int i915_init_mem_type(drm_device_t *dev, uint32_t type, + drm_mem_type_manager_t *man); +extern uint32_t i915_evict_flags(drm_device_t *dev, uint32_t type); +extern int i915_move(drm_buffer_object_t *bo, int evict, + int no_wait, drm_bo_mem_reg_t *new_mem); + #endif #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) @@ -331,6 +341,7 @@ extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller); #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) +#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) |