diff options
Diffstat (limited to 'shared-core')
| -rw-r--r-- | shared-core/nv04_graph.c | 15 | ||||
| -rw-r--r-- | shared-core/nv30_graph.c | 29 | ||||
| -rw-r--r-- | shared-core/nv40_graph.c | 147 |
3 files changed, 170 insertions, 21 deletions
diff --git a/shared-core/nv04_graph.c b/shared-core/nv04_graph.c index 213696ca..f1117cd6 100644 --- a/shared-core/nv04_graph.c +++ b/shared-core/nv04_graph.c @@ -358,14 +358,15 @@ void nouveau_nv04_context_switch(struct drm_device *dev) chid = (NV_READ(NV04_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); last = dev_priv->fifos[chid]; - DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n",last->id, next->id); + DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",last->id, next->id); - NV_WRITE(NV03_PFIFO_CACHES, 0x0); +/* NV_WRITE(NV03_PFIFO_CACHES, 0x0); NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0); - NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x0); + NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x0);*/ NV_WRITE(NV04_PGRAPH_FIFO,0x0); - nv04_graph_save_context(last); + if (last) + nv04_graph_save_context(last); nouveau_wait_for_idle(dev); @@ -374,16 +375,16 @@ void nouveau_nv04_context_switch(struct drm_device *dev) nouveau_wait_for_idle(dev); - nv04_graph_load_context(last); + nv04_graph_load_context(next); NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10010100); NV_WRITE(NV04_PGRAPH_CTX_USER, next->id << 24); NV_WRITE(NV04_PGRAPH_FFINTFC_ST2, NV_READ(NV04_PGRAPH_FFINTFC_ST2)&0x000FFFFF); - NV_WRITE(NV04_PGRAPH_FIFO,0x0); +/* NV_WRITE(NV04_PGRAPH_FIFO,0x0); NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0); NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x1); - NV_WRITE(NV03_PFIFO_CACHES, 0x1); + NV_WRITE(NV03_PFIFO_CACHES, 0x1);*/ NV_WRITE(NV04_PGRAPH_FIFO,0x1); } diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c index ca43bb95..590a5c33 100644 --- a/shared-core/nv30_graph.c +++ b/shared-core/nv30_graph.c @@ -8,9 +8,8 @@ #include "nouveau_drm.h" /* - * There are 4 families : - * NV30 is 0x10de:0x030* (not working, no dump for that one) - * + * There are 3 families : + * NV30 is 0x10de:0x030* * NV31 is 0x10de:0x031* * * NV34 is 0x10de:0x032* @@ -25,11 +24,11 @@ */ -#define NV31_GRCTX_SIZE (22392) -#define NV34_GRCTX_SIZE (18140) -#define NV35_GRCTX_SIZE (22396) +#define NV30_31_GRCTX_SIZE (22392) +#define NV34_GRCTX_SIZE (18140) +#define NV35_36_GRCTX_SIZE (22396) -static void nv31_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) +static void nv30_31_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) { struct drm_nouveau_private *dev_priv = dev->dev_private; int i; @@ -919,7 +918,8 @@ static void nv31_graph_context_init(struct drm_device *dev, struct nouveau_gpuob INSTANCE_WR(ctx, 0x3858/4, 0x40000000); INSTANCE_WR(ctx, 0x385c/4, 0x3f800000); INSTANCE_WR(ctx, 0x3864/4, 0xbf800000); - INSTANCE_WR(ctx, 0x386c/4, 0xbf800000);} + INSTANCE_WR(ctx, 0x386c/4, 0xbf800000); +} static void nv34_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) { @@ -1814,7 +1814,7 @@ static void nv34_graph_context_init(struct drm_device *dev, struct nouveau_gpuob INSTANCE_WR(ctx, 0x2f00/4, 0xbf800000); } -static void nv35_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) +static void nv35_36_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) { struct drm_nouveau_private *dev_priv = dev->dev_private; int i; @@ -2715,9 +2715,10 @@ int nv30_graph_create_context(struct nouveau_channel *chan) int ret; switch (dev_priv->chipset) { + case 0x30: case 0x31: - ctx_size = NV31_GRCTX_SIZE; - ctx_init = nv31_graph_context_init; + ctx_size = NV30_31_GRCTX_SIZE; + ctx_init = nv30_31_graph_context_init; break; case 0x34: ctx_size = NV34_GRCTX_SIZE; @@ -2725,12 +2726,12 @@ int nv30_graph_create_context(struct nouveau_channel *chan) break; case 0x35: case 0x36: - ctx_size = NV35_GRCTX_SIZE; - ctx_init = nv35_graph_context_init; + ctx_size = NV35_36_GRCTX_SIZE; + ctx_init = nv35_36_graph_context_init; break; default: ctx_size = 0; - ctx_init = nv35_graph_context_init; + ctx_init = nv35_36_graph_context_init; DRM_ERROR("Please contact the devs if you want your NV%x card to work\n",dev_priv->chipset); break; } diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c index 26237c7d..99c77cb9 100644 --- a/shared-core/nv40_graph.c +++ b/shared-core/nv40_graph.c @@ -34,6 +34,7 @@ * between the contexts */ #define NV40_GRCTX_SIZE (175*1024) +#define NV41_GRCTX_SIZE (92*1024) #define NV43_GRCTX_SIZE (70*1024) #define NV46_GRCTX_SIZE (70*1024) /* probably ~64KiB */ #define NV49_GRCTX_SIZE (164640) @@ -188,6 +189,116 @@ nv40_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) } static void +nv41_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + int i; + + INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); + INSTANCE_WR(ctx, 0x00000024/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x00000028/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x00000030/4, 0x00000001); + INSTANCE_WR(ctx, 0x0000011c/4, 0x20010001); + INSTANCE_WR(ctx, 0x00000120/4, 0x0f73ef00); + INSTANCE_WR(ctx, 0x00000128/4, 0x02008821); + for (i = 0x00000178; i <= 0x00000180; i += 4) + INSTANCE_WR(ctx, i/4, 0x00000040); + INSTANCE_WR(ctx, 0x00000188/4, 0x00000040); + for (i = 0x00000194; i <= 0x000001b0; i += 4) + INSTANCE_WR(ctx, i/4, 0x80000000); + INSTANCE_WR(ctx, 0x000001d0/4, 0x0b0b0b0c); + INSTANCE_WR(ctx, 0x00000340/4, 0x00040000); + for (i = 0x00000350; i <= 0x0000035c; i += 4) + INSTANCE_WR(ctx, i/4, 0x55555555); + INSTANCE_WR(ctx, 0x00000388/4, 0x00000008); + INSTANCE_WR(ctx, 0x0000039c/4, 0x00001010); + INSTANCE_WR(ctx, 0x000003cc/4, 0x00000111); + INSTANCE_WR(ctx, 0x000003d0/4, 0x00080060); + INSTANCE_WR(ctx, 0x000003ec/4, 0x00000080); + INSTANCE_WR(ctx, 0x000003f0/4, 0xffff0000); + INSTANCE_WR(ctx, 0x000003f4/4, 0x00000001); + INSTANCE_WR(ctx, 0x00000408/4, 0x46400000); + INSTANCE_WR(ctx, 0x00000418/4, 0xffff0000); + INSTANCE_WR(ctx, 0x00000424/4, 0x0fff0000); + INSTANCE_WR(ctx, 0x00000428/4, 0x0fff0000); + INSTANCE_WR(ctx, 0x00000430/4, 0x00011100); + for (i = 0x0000044c; i <= 0x00000488; i += 4) + INSTANCE_WR(ctx, i/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x00000494/4, 0x4b7fffff); + INSTANCE_WR(ctx, 0x000004bc/4, 0x30201000); + INSTANCE_WR(ctx, 0x000004c0/4, 0x70605040); + INSTANCE_WR(ctx, 0x000004c4/4, 0xb8a89888); + INSTANCE_WR(ctx, 0x000004c8/4, 0xf8e8d8c8); + INSTANCE_WR(ctx, 0x000004dc/4, 0x40100000); + INSTANCE_WR(ctx, 0x000004f8/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x0000052c/4, 0x435185d6); + INSTANCE_WR(ctx, 0x00000530/4, 0x2155b699); + INSTANCE_WR(ctx, 0x00000534/4, 0xfedcba98); + INSTANCE_WR(ctx, 0x00000538/4, 0x00000098); + INSTANCE_WR(ctx, 0x00000548/4, 0xffffffff); + INSTANCE_WR(ctx, 0x0000054c/4, 0x00ff7000); + INSTANCE_WR(ctx, 0x00000550/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x00000560/4, 0x00ff0000); + INSTANCE_WR(ctx, 0x00000598/4, 0x00ffff00); + for (i = 0x000005dc; i <= 0x00000618; i += 4) + INSTANCE_WR(ctx, i/4, 0x00018488); + for (i = 0x0000061c; i <= 0x00000658; i += 4) + INSTANCE_WR(ctx, i/4, 0x00028202); + for (i = 0x0000069c; i <= 0x000006d8; i += 4) + INSTANCE_WR(ctx, i/4, 0x0000aae4); + for (i = 0x000006dc; i <= 0x00000718; i += 4) + INSTANCE_WR(ctx, i/4, 0x01012000); + for (i = 0x0000071c; i <= 0x00000758; i += 4) + INSTANCE_WR(ctx, i/4, 0x00080008); + for (i = 0x0000079c; i <= 0x000007d8; i += 4) + INSTANCE_WR(ctx, i/4, 0x00100008); + for (i = 0x0000082c; i <= 0x00000838; i += 4) + INSTANCE_WR(ctx, i/4, 0x0001bc80); + for (i = 0x0000083c; i <= 0x00000848; i += 4) + INSTANCE_WR(ctx, i/4, 0x00000202); + for (i = 0x0000085c; i <= 0x00000868; i += 4) + INSTANCE_WR(ctx, i/4, 0x00000008); + for (i = 0x0000087c; i <= 0x00000888; i += 4) + INSTANCE_WR(ctx, i/4, 0x00080008); + INSTANCE_WR(ctx, 0x0000089c/4, 0x00000002); + INSTANCE_WR(ctx, 0x000008d0/4, 0x00000021); + INSTANCE_WR(ctx, 0x000008d4/4, 0x030c30c3); + INSTANCE_WR(ctx, 0x000008e0/4, 0x3e020200); + INSTANCE_WR(ctx, 0x000008e4/4, 0x00ffffff); + INSTANCE_WR(ctx, 0x000008e8/4, 0x20103f00); + INSTANCE_WR(ctx, 0x000008f4/4, 0x00020000); + INSTANCE_WR(ctx, 0x0000092c/4, 0x00008100); + INSTANCE_WR(ctx, 0x000009b8/4, 0x00000001); + INSTANCE_WR(ctx, 0x000009fc/4, 0x00001001); + INSTANCE_WR(ctx, 0x00000a04/4, 0x00000003); + INSTANCE_WR(ctx, 0x00000a08/4, 0x00888001); + INSTANCE_WR(ctx, 0x00000aac/4, 0x00000005); + INSTANCE_WR(ctx, 0x00000ab8/4, 0x0000ffff); + for (i = 0x00000ad4; i <= 0x00000ae4; i += 4) + INSTANCE_WR(ctx, i/4, 0x00005555); + INSTANCE_WR(ctx, 0x00000ae8/4, 0x00000001); + INSTANCE_WR(ctx, 0x00000b20/4, 0x00000001); + for (i = 0x00002ee8; i <= 0x00002f60; i += 8) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for (i = 0x00005168; i <= 0x00007358; i += 24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for (i = 0x00007368; i <= 0x00007758; i += 16) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for (i = 0x0000a068; i <= 0x0000c258; i += 24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for (i = 0x0000c268; i <= 0x0000c658; i += 16) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for (i = 0x0000ef68; i <= 0x00011158; i += 24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for (i = 0x00011168; i <= 0x00011558; i += 16) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for (i = 0x00013e68; i <= 0x00016058; i += 24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for (i = 0x00016068; i <= 0x00016458; i += 16) + INSTANCE_WR(ctx, i/4, 0x3f800000); +}; + +static void nv43_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) { struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -1237,6 +1348,10 @@ nv40_graph_create_context(struct nouveau_channel *chan) ctx_size = NV40_GRCTX_SIZE; ctx_init = nv40_graph_context_init; break; + case 0x41: + ctx_size = NV41_GRCTX_SIZE; + ctx_init = nv41_graph_context_init; + break; case 0x43: ctx_size = NV43_GRCTX_SIZE; ctx_init = nv43_graph_context_init; @@ -1431,6 +1546,37 @@ static uint32_t nv40_ctx_voodoo[] = { ~0 }; +static uint32_t nv41_ctx_voodoo[] = { + 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001, + 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00408f65, 0x00409306, + 0x0040a068, 0x0040198f, 0x00200001, 0x0060000a, 0x00700080, 0x00104042, + 0x00200001, 0x0060000a, 0x00700000, 0x001040c5, 0x00401826, 0x00401968, + 0x0060000d, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080, + 0x004020e6, 0x007000a0, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d, + 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4, + 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e, + 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143, + 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10, + 0x001046ec, 0x00500060, 0x00404087, 0x0060000d, 0x004079e6, 0x002000f1, + 0x0060000a, 0x00148653, 0x00104668, 0x0010c66d, 0x00120682, 0x0011068b, + 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6, + 0x00200020, 0x001006cc, 0x001046ed, 0x001246f0, 0x002000c0, 0x00100700, + 0x0010c3d7, 0x001043e1, 0x00500060, 0x00200233, 0x0060000a, 0x00104800, + 0x00108901, 0x00124920, 0x0020001f, 0x00100940, 0x00140965, 0x00148a00, + 0x00108a14, 0x00200020, 0x00100b00, 0x00134b2c, 0x0010cd00, 0x0010cd04, + 0x00114d08, 0x00104d80, 0x00104e00, 0x0012d600, 0x00105c00, 0x00104f06, + 0x002002d2, 0x0060000a, 0x00300000, 0x00200680, 0x00407200, 0x00200684, + 0x00800001, 0x00200b1a, 0x0060000a, 0x00206380, 0x0040788a, 0x00201480, + 0x00800041, 0x00408900, 0x00600006, 0x004085e6, 0x00700080, 0x0020007a, + 0x0060000a, 0x00104280, 0x002002d2, 0x0060000a, 0x00200004, 0x00800001, + 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x0040a068, 0x00700000, + 0x00200000, 0x0060000a, 0x00106002, 0x00700080, 0x00400a68, 0x00500060, + 0x00600007, 0x00409388, 0x0060000f, 0x00500060, 0x00200000, 0x0060000a, + 0x00700000, 0x00106001, 0x00910880, 0x00901ffe, 0x00940400, 0x00200020, + 0x0060000b, 0x00500069, 0x0060000c, 0x00402168, 0x0040a206, 0x0040a305, + 0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0 +}; + static uint32_t nv43_ctx_voodoo[] = { 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001, 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409565, 0x00409a06, @@ -1683,6 +1829,7 @@ nv40_graph_init(struct drm_device *dev) switch (dev_priv->chipset) { case 0x40: ctx_voodoo = nv40_ctx_voodoo; break; + case 0x41: ctx_voodoo = nv41_ctx_voodoo; break; case 0x43: ctx_voodoo = nv43_ctx_voodoo; break; case 0x44: ctx_voodoo = nv44_ctx_voodoo; break; case 0x46: ctx_voodoo = nv46_ctx_voodoo; break; |