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-rw-r--r--shared-core/drm.h11
-rw-r--r--shared-core/drm_pciids.txt1
-rw-r--r--shared-core/i915_dma.c34
-rw-r--r--shared-core/i915_irq.c16
-rw-r--r--shared-core/mach64_dma.c3
-rw-r--r--shared-core/mga_dma.c3
-rw-r--r--shared-core/nouveau_drm.h2
-rw-r--r--shared-core/nouveau_fifo.c14
-rw-r--r--shared-core/nouveau_irq.c1
-rw-r--r--shared-core/nouveau_mem.c2
-rw-r--r--shared-core/nv10_graph.c4
-rw-r--r--shared-core/r128_cce.c3
-rw-r--r--shared-core/r300_cmdbuf.c26
-rw-r--r--shared-core/r300_reg.h13
-rw-r--r--shared-core/radeon_cp.c2
-rw-r--r--shared-core/radeon_drv.h1
-rw-r--r--shared-core/radeon_state.c46
-rw-r--r--shared-core/savage_bci.c2
-rw-r--r--shared-core/via_map.c2
19 files changed, 109 insertions, 77 deletions
diff --git a/shared-core/drm.h b/shared-core/drm.h
index 890dcf88..0f4a878b 100644
--- a/shared-core/drm.h
+++ b/shared-core/drm.h
@@ -80,14 +80,7 @@
#define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE
#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__)
-#if (defined(__FreeBSD__) || defined(__FreeBSD_kernel__)) && defined(IN_MODULE)
-/* Prevent name collision when including sys/ioccom.h */
-#undef ioctl
#include <sys/ioccom.h>
-#define ioctl(a,b,c) xf86ioctl(a,b,c)
-#else
-#include <sys/ioccom.h>
-#endif /* __FreeBSD__ && xf86ioctl */
#define DRM_IOCTL_NR(n) ((n) & 0xff)
#define DRM_IOC_VOID IOC_VOID
#define DRM_IOC_READ IOC_OUT
@@ -796,9 +789,9 @@ typedef struct drm_fence_arg {
typedef enum {
drm_bo_type_dc,
- drm_bo_type_kernel, /* for initial kernel allocations */
drm_bo_type_user,
- drm_bo_type_fake
+ drm_bo_type_fake,
+ drm_bo_type_kernel, /* for initial kernel allocations */
}drm_bo_type_t;
diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt
index f090489f..ad67dda2 100644
--- a/shared-core/drm_pciids.txt
+++ b/shared-core/drm_pciids.txt
@@ -187,7 +187,6 @@
0x1002 0x4c51 0 "3D Rage LT Pro"
0x1002 0x4c42 0 "3D Rage LT Pro AGP-133"
0x1002 0x4c44 0 "3D Rage LT Pro AGP-66"
-0x1002 0x4759 0 "Rage 3D IICATI 3D RAGE IIC AGP(A12/A13)"
0x1002 0x474c 0 "Rage XC"
0x1002 0x474f 0 "Rage XL"
0x1002 0x4752 0 "Rage XL"
diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c
index f4761da9..a5e51de4 100644
--- a/shared-core/i915_dma.c
+++ b/shared-core/i915_dma.c
@@ -98,10 +98,13 @@ static int i915_initialize(drm_device_t * dev,
drm_i915_private_t * dev_priv,
drm_i915_init_t * init)
{
-
- /* reset ring pointers */
- I915_WRITE(LP_RING + RING_LEN, 0);
- mb();
+ dev_priv->sarea = drm_getsarea(dev);
+ if (!dev_priv->sarea) {
+ DRM_ERROR("can not find sarea!\n");
+ dev->dev_private = (void *)dev_priv;
+ i915_dma_cleanup(dev);
+ return DRM_ERR(EINVAL);
+ }
memset((void *)(dev_priv->ring.virtual_start), 0, dev_priv->ring.Size);
@@ -121,6 +124,29 @@ static int i915_initialize(drm_device_t * dev,
*/
dev_priv->allow_batchbuffer = 1;
+ /* Enable vblank on pipe A for older X servers
+ */
+ dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
+
+ /* Program Hardware Status Page */
+ dev_priv->status_page_dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE,
+ 0xffffffff);
+
+ if (!dev_priv->status_page_dmah) {
+ dev->dev_private = (void *)dev_priv;
+ i915_dma_cleanup(dev);
+ DRM_ERROR("Can not allocate hardware status page\n");
+ return DRM_ERR(ENOMEM);
+ }
+ dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
+ dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
+
+ memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
+ DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
+
+ I915_WRITE(0x02080, dev_priv->dma_status_page);
+ DRM_DEBUG("Enabled hardware status page\n");
+ dev->dev_private = (void *)dev_priv;
return 0;
}
diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c
index 870fe402..4ceed3e3 100644
--- a/shared-core/i915_irq.c
+++ b/shared-core/i915_irq.c
@@ -381,6 +381,13 @@ void i915_user_irq_off(drm_i915_private_t *dev_priv)
spin_unlock(&dev_priv->user_irq_lock);
}
+static int wait_compare(struct drm_device *dev, void *priv)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ int irq_nr = (u64)priv;
+
+ return (READ_BREADCRUMB(dev_priv) >= irq_nr);
+}
static int i915_wait_irq(drm_device_t * dev, int irq_nr)
{
@@ -396,8 +403,8 @@ static int i915_wait_irq(drm_device_t * dev, int irq_nr)
dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
i915_user_irq_on(dev_priv);
- DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
- READ_BREADCRUMB(dev_priv) >= irq_nr);
+ ret = drm_wait_on(dev, &dev_priv->irq_queue, 3 * DRM_HZ, wait_compare,
+ (void *)(u64)irq_nr);
i915_user_irq_off(dev_priv);
if (ret == DRM_ERR(EBUSY)) {
@@ -719,9 +726,6 @@ void i915_driver_irq_postinstall(drm_device_t * dev)
INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
dev_priv->swaps_pending = 0;
- if (!dev_priv->vblank_pipe)
- dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
-
dev_priv->swaps_lock = SPIN_LOCK_UNLOCKED;
INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
dev_priv->swaps_pending = 0;
@@ -729,8 +733,6 @@ void i915_driver_irq_postinstall(drm_device_t * dev)
dev_priv->user_irq_lock = SPIN_LOCK_UNLOCKED;
dev_priv->user_irq_refcount = 0;
- if (!dev_priv->vblank_pipe)
- dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
i915_enable_interrupt(dev);
DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
diff --git a/shared-core/mach64_dma.c b/shared-core/mach64_dma.c
index 3a5fdee8..60f55900 100644
--- a/shared-core/mach64_dma.c
+++ b/shared-core/mach64_dma.c
@@ -792,8 +792,7 @@ static int mach64_do_dma_init(drm_device_t * dev, drm_mach64_init_t * init)
INIT_LIST_HEAD(&dev_priv->placeholders);
INIT_LIST_HEAD(&dev_priv->pending);
- DRM_GETSAREA();
-
+ dev_priv->sarea = drm_getsarea(dev);
if (!dev_priv->sarea) {
DRM_ERROR("can not find sarea!\n");
dev->dev_private = (void *)dev_priv;
diff --git a/shared-core/mga_dma.c b/shared-core/mga_dma.c
index e6468d67..78448282 100644
--- a/shared-core/mga_dma.c
+++ b/shared-core/mga_dma.c
@@ -830,8 +830,7 @@ static int mga_do_init_dma(drm_device_t * dev, drm_mga_init_t * init)
dev_priv->texture_offset = init->texture_offset[0];
dev_priv->texture_size = init->texture_size[0];
- DRM_GETSAREA();
-
+ dev_priv->sarea = drm_getsarea(dev);
if (!dev_priv->sarea) {
DRM_ERROR("failed to find sarea!\n");
return DRM_ERR(EINVAL);
diff --git a/shared-core/nouveau_drm.h b/shared-core/nouveau_drm.h
index 3ba7e961..1e7322e0 100644
--- a/shared-core/nouveau_drm.h
+++ b/shared-core/nouveau_drm.h
@@ -114,7 +114,7 @@ enum nouveau_card_type {
NV_10 =10,
NV_11 =10,
NV_15 =10,
- NV_17 =10,
+ NV_17 =17,
NV_20 =20,
NV_25 =20,
NV_30 =30,
diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c
index 92166eeb..8e66ca2e 100644
--- a/shared-core/nouveau_fifo.c
+++ b/shared-core/nouveau_fifo.c
@@ -51,7 +51,7 @@ int nouveau_fifo_ctx_size(drm_device_t* dev)
if (dev_priv->card_type >= NV_40)
return 128;
- else if (dev_priv->card_type >= NV_10)
+ else if (dev_priv->card_type >= NV_17)
return 64;
else
return 32;
@@ -90,10 +90,12 @@ static int nouveau_fifo_instmem_configure(drm_device_t *dev)
break;
case NV_30:
case NV_20:
- case NV_10:
+ case NV_17:
NV_WRITE(NV03_PFIFO_RAMFC, (dev_priv->ramfc_offset>>8) |
(1 << 16) /* 64 Bytes entry*/);
+ /* XXX nvidia blob set bit 18, 21,23 for nv20 & nv30 */
break;
+ case NV_10:
case NV_04:
case NV_03:
NV_WRITE(NV03_PFIFO_RAMFC, dev_priv->ramfc_offset>>8);
@@ -269,11 +271,12 @@ static void nouveau_nv10_context_init(drm_device_t *dev, int channel)
drm_nouveau_private_t *dev_priv = dev->dev_private;
struct nouveau_object *cb_obj;
uint32_t fifoctx;
+ int ctx_size = nouveau_fifo_ctx_size(dev);
int i;
cb_obj = dev_priv->fifos[channel].cmdbuf_obj;
- fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*64;
+ fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*ctx_size;
- for (i=0;i<64;i+=4)
+ for (i=0;i<ctx_size;i+=4)
NV_WRITE(fifoctx + i, 0);
/* Fill entries that are seen filled in dumps of nvidia driver just
@@ -327,6 +330,7 @@ static void nouveau_nv30_context_init(drm_device_t *dev, int channel)
RAMFC_WR(SEMAPHORE, NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
}
+#if 0
static void nouveau_nv10_context_save(drm_device_t *dev)
{
drm_nouveau_private_t *dev_priv = dev->dev_private;
@@ -350,6 +354,7 @@ static void nouveau_nv10_context_save(drm_device_t *dev)
RAMFC_WR(SEMAPHORE , NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV10_PFIFO_CACHE1_DMA_SUBROUTINE));
}
+#endif
#undef RAMFC_WR
#define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV40_RAMFC_##offset, (val))
@@ -507,6 +512,7 @@ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp)
nouveau_nv04_context_init(dev, channel);
break;
case NV_10:
+ case NV_17:
nv10_graph_context_create(dev, channel);
nouveau_nv10_context_init(dev, channel);
break;
diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c
index b7c1d532..8de6e705 100644
--- a/shared-core/nouveau_irq.c
+++ b/shared-core/nouveau_irq.c
@@ -372,6 +372,7 @@ static void nouveau_pgraph_irq_handler(drm_device_t *dev)
nouveau_nv04_context_switch(dev);
break;
case NV_10:
+ case NV_17:
nouveau_nv10_context_switch(dev);
break;
case NV_20:
diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c
index 541f1545..a5343b99 100644
--- a/shared-core/nouveau_mem.c
+++ b/shared-core/nouveau_mem.c
@@ -248,6 +248,7 @@ uint64_t nouveau_mem_fb_amount(struct drm_device *dev)
}
break;
case NV_10:
+ case NV_17:
case NV_20:
case NV_30:
case NV_40:
@@ -521,6 +522,7 @@ nouveau_instmem_configure_fixed_tables(struct drm_device *dev)
break;
case NV_30:
case NV_20:
+ case NV_17:
case NV_10:
case NV_04:
case NV_03:
diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c
index 4cc44e21..fb189709 100644
--- a/shared-core/nv10_graph.c
+++ b/shared-core/nv10_graph.c
@@ -640,6 +640,10 @@ int nv10_graph_context_create(drm_device_t *dev, int channel) {
NV_WRITE_CTX(NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
NV_WRITE_CTX(NV04_PGRAPH_BETA_AND , 0xFFFFFFFF);
+ NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
+ NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
+ NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
+ NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
NV_WRITE_CTX(NV03_PGRAPH_XY_LOGIC_MISC0, 0x0001ffff);
/* is it really needed ??? */
diff --git a/shared-core/r128_cce.c b/shared-core/r128_cce.c
index fc7bb8fc..a2ee18b7 100644
--- a/shared-core/r128_cce.c
+++ b/shared-core/r128_cce.c
@@ -456,8 +456,7 @@ static int r128_do_init_cce(drm_device_t * dev, drm_r128_init_t * init)
dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
(dev_priv->span_offset >> 5));
- DRM_GETSAREA();
-
+ dev_priv->sarea = drm_getsarea(dev);
if (!dev_priv->sarea) {
DRM_ERROR("could not find sarea!\n");
dev->dev_private = (void *)dev_priv;
diff --git a/shared-core/r300_cmdbuf.c b/shared-core/r300_cmdbuf.c
index 667a829b..d3c52d43 100644
--- a/shared-core/r300_cmdbuf.c
+++ b/shared-core/r300_cmdbuf.c
@@ -148,15 +148,15 @@ void r300_init_reg_flags(void)
/* these match cmducs() command in r300_driver/r300/r300_cmdbuf.c */
ADD_RANGE(R300_SE_VPORT_XSCALE, 6);
- ADD_RANGE(0x2080, 1);
+ ADD_RANGE(R300_VAP_CNTL, 1);
ADD_RANGE(R300_SE_VTE_CNTL, 2);
ADD_RANGE(0x2134, 2);
- ADD_RANGE(0x2140, 1);
+ ADD_RANGE(R300_VAP_CNTL_STATUS, 1);
ADD_RANGE(R300_VAP_INPUT_CNTL_0, 2);
ADD_RANGE(0x21DC, 1);
- ADD_RANGE(0x221C, 1);
+ ADD_RANGE(R300_VAP_UNKNOWN_221C, 1);
ADD_RANGE(0x2220, 4);
- ADD_RANGE(0x2288, 1);
+ ADD_RANGE(R300_VAP_UNKNOWN_2288, 1);
ADD_RANGE(R300_VAP_OUTPUT_VTX_FMT_0, 2);
ADD_RANGE(R300_VAP_PVS_CNTL_1, 3);
ADD_RANGE(R300_GB_ENABLE, 1);
@@ -168,13 +168,13 @@ void r300_init_reg_flags(void)
ADD_RANGE(R300_RE_POINTSIZE, 1);
ADD_RANGE(0x4230, 3);
ADD_RANGE(R300_RE_LINE_CNT, 1);
- ADD_RANGE(0x4238, 1);
+ ADD_RANGE(R300_RE_UNK4238, 1);
ADD_RANGE(0x4260, 3);
- ADD_RANGE(0x4274, 4);
- ADD_RANGE(0x4288, 5);
- ADD_RANGE(0x42A0, 1);
+ ADD_RANGE(R300_RE_SHADE, 4);
+ ADD_RANGE(R300_RE_POLYGON_MODE, 5);
+ ADD_RANGE(R300_RE_ZBIAS_CNTL, 1);
ADD_RANGE(R300_RE_ZBIAS_T_FACTOR, 4);
- ADD_RANGE(0x42B4, 1);
+ ADD_RANGE(R300_RE_OCCLUSION_CNTL, 1);
ADD_RANGE(R300_RE_CULL_CNTL, 1);
ADD_RANGE(0x42C0, 2);
ADD_RANGE(R300_RS_CNTL_0, 2);
@@ -190,22 +190,22 @@ void r300_init_reg_flags(void)
ADD_RANGE(R300_PFS_INSTR1_0, 64);
ADD_RANGE(R300_PFS_INSTR2_0, 64);
ADD_RANGE(R300_PFS_INSTR3_0, 64);
- ADD_RANGE(0x4BC0, 1);
- ADD_RANGE(0x4BC8, 3);
+ ADD_RANGE(R300_RE_FOG_STATE, 1);
+ ADD_RANGE(R300_FOG_COLOR_R, 3);
ADD_RANGE(R300_PP_ALPHA_TEST, 2);
ADD_RANGE(0x4BD8, 1);
ADD_RANGE(R300_PFS_PARAM_0_X, 64);
ADD_RANGE(0x4E00, 1);
ADD_RANGE(R300_RB3D_CBLEND, 2);
ADD_RANGE(R300_RB3D_COLORMASK, 1);
- ADD_RANGE(0x4E10, 3);
+ ADD_RANGE(R300_RB3D_BLEND_COLOR, 3);
ADD_RANGE_MARK(R300_RB3D_COLOROFFSET0, 1, MARK_CHECK_OFFSET); /* check offset */
ADD_RANGE(R300_RB3D_COLORPITCH0, 1);
ADD_RANGE(0x4E50, 9);
ADD_RANGE(0x4E88, 1);
ADD_RANGE(0x4EA0, 2);
ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3);
- ADD_RANGE(0x4F10, 4);
+ ADD_RANGE(R300_RB3D_ZSTENCIL_FORMAT, 4);
ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */
ADD_RANGE(R300_RB3D_DEPTHPITCH, 1);
ADD_RANGE(0x4F28, 1);
diff --git a/shared-core/r300_reg.h b/shared-core/r300_reg.h
index 1f65f9a7..0a31f0b9 100644
--- a/shared-core/r300_reg.h
+++ b/shared-core/r300_reg.h
@@ -23,6 +23,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
+/* *INDENT-OFF* */
+
#ifndef _R300_REG_H
#define _R300_REG_H
@@ -145,6 +147,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R300_VC_NO_SWAP (0 << 0)
# define R300_VC_16BIT_SWAP (1 << 0)
# define R300_VC_32BIT_SWAP (2 << 0)
+# define R300_VAP_TCL_BYPASS (1 << 8)
/* gap */
@@ -487,6 +490,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R300_GB_W_SELECT_1 (1<<4)
#define R300_GB_AA_CONFIG 0x4020
+# define R300_AA_DISABLE 0x00
# define R300_AA_ENABLE 0x01
# define R300_AA_SUBSAMPLES_2 0
# define R300_AA_SUBSAMPLES_3 (1<<1)
@@ -669,6 +673,11 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
/* Special handling for color: When the fragment program uses color,
* the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the
* color register index.
+ *
+ * Apperently you may set the R300_RS_ROUTE_0_COLOR bit, but not provide any
+ * R300_RS_ROUTE_0_COLOR_DEST value; this setup is used for clearing the state.
+ * See r300_ioctl.c:r300EmitClearState. I'm not sure if this setup is strictly
+ * correct or not. - Oliver.
*/
# define R300_RS_ROUTE_0_COLOR (1 << 14)
# define R300_RS_ROUTE_0_COLOR_DEST_SHIFT 17
@@ -1553,6 +1562,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#define R300_PRIM_COLOR_ORDER_BGRA (0 << 6)
#define R300_PRIM_COLOR_ORDER_RGBA (1 << 6)
#define R300_PRIM_NUM_VERTICES_SHIFT 16
+#define R300_PRIM_NUM_VERTICES_MASK 0xffff
/* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR.
* Two parameter dwords:
@@ -1601,5 +1611,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#define R300_CP_CMD_BITBLT_MULTI 0xC0009B00
-
#endif /* _R300_REG_H */
+
+/* *INDENT-ON* */
diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c
index bfc2d088..bde98b30 100644
--- a/shared-core/radeon_cp.c
+++ b/shared-core/radeon_cp.c
@@ -1505,13 +1505,13 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
RADEON_ROUND_MODE_TRUNC |
RADEON_ROUND_PREC_8TH_PIX);
- DRM_GETSAREA();
dev_priv->ring_offset = init->ring_offset;
dev_priv->ring_rptr_offset = init->ring_rptr_offset;
dev_priv->buffers_offset = init->buffers_offset;
dev_priv->gart_textures_offset = init->gart_textures_offset;
+ dev_priv->sarea = drm_getsarea(dev);
if (!dev_priv->sarea) {
DRM_ERROR("could not find sarea!\n");
radeon_do_cleanup_cp(dev);
diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 00646c8f..4a36ea70 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -245,7 +245,6 @@ typedef struct drm_radeon_private {
int do_boxes;
int page_flipping;
- int current_page;
u32 color_fmt;
unsigned int front_offset;
diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c
index b95549d8..bad054d7 100644
--- a/shared-core/radeon_state.c
+++ b/shared-core/radeon_state.c
@@ -773,7 +773,7 @@ static void radeon_clear_box(drm_radeon_private_t * dev_priv,
RADEON_GMC_SRC_DATATYPE_COLOR |
RADEON_ROP3_P | RADEON_GMC_CLR_CMP_CNTL_DIS);
- if (dev_priv->page_flipping && dev_priv->current_page == 1) {
+ if (dev_priv->sarea_priv->pfCurrentPage == 1) {
OUT_RING(dev_priv->front_pitch_offset);
} else {
OUT_RING(dev_priv->back_pitch_offset);
@@ -861,7 +861,7 @@ static void radeon_cp_dispatch_clear(drm_device_t * dev,
dev_priv->stats.clears++;
- if (dev_priv->page_flipping && dev_priv->current_page == 1) {
+ if (dev_priv->sarea_priv->pfCurrentPage == 1) {
unsigned int tmp = flags;
flags &= ~(RADEON_FRONT | RADEON_BACK);
@@ -1382,7 +1382,7 @@ static void radeon_cp_dispatch_swap(drm_device_t * dev)
/* Make this work even if front & back are flipped:
*/
OUT_RING(CP_PACKET0(RADEON_SRC_PITCH_OFFSET, 1));
- if (dev_priv->current_page == 0) {
+ if (dev_priv->sarea_priv->pfCurrentPage == 0) {
OUT_RING(dev_priv->back_pitch_offset);
OUT_RING(dev_priv->front_pitch_offset);
} else {
@@ -1416,12 +1416,12 @@ static void radeon_cp_dispatch_flip(drm_device_t * dev)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_sarea_t *sarea = (drm_sarea_t *) dev_priv->sarea->handle;
- int offset = (dev_priv->current_page == 1)
+ int offset = (dev_priv->sarea_priv->pfCurrentPage == 1)
? dev_priv->front_offset : dev_priv->back_offset;
RING_LOCALS;
- DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
+ DRM_DEBUG("%s: pfCurrentPage=%d\n",
__FUNCTION__,
- dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage);
+ dev_priv->sarea_priv->pfCurrentPage);
/* Do some trivial performance monitoring...
*/
@@ -1449,8 +1449,8 @@ static void radeon_cp_dispatch_flip(drm_device_t * dev)
* performing the swapbuffer ioctl.
*/
dev_priv->sarea_priv->last_frame++;
- dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
- 1 - dev_priv->current_page;
+ dev_priv->sarea_priv->pfCurrentPage =
+ 1 - dev_priv->sarea_priv->pfCurrentPage;
BEGIN_RING(2);
@@ -2162,24 +2162,10 @@ static int radeon_do_init_pageflip(drm_device_t * dev)
ADVANCE_RING();
dev_priv->page_flipping = 1;
- dev_priv->current_page = 0;
- dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
- return 0;
-}
-
-/* Called whenever a client dies, from drm_release.
- * NOTE: Lock isn't necessarily held when this is called!
- */
-static int radeon_do_cleanup_pageflip(drm_device_t * dev)
-{
- drm_radeon_private_t *dev_priv = dev->dev_private;
- DRM_DEBUG("\n");
+ if (dev_priv->sarea_priv->pfCurrentPage != 1)
+ dev_priv->sarea_priv->pfCurrentPage = 0;
- if (dev_priv->current_page != 0)
- radeon_cp_dispatch_flip(dev);
-
- dev_priv->page_flipping = 0;
return 0;
}
@@ -3225,9 +3211,7 @@ void radeon_driver_preclose(drm_device_t * dev, DRMFILE filp)
{
if (dev->dev_private) {
drm_radeon_private_t *dev_priv = dev->dev_private;
- if (dev_priv->page_flipping) {
- radeon_do_cleanup_pageflip(dev);
- }
+ dev_priv->page_flipping = 0;
radeon_mem_release(filp, dev_priv->gart_heap);
radeon_mem_release(filp, dev_priv->fb_heap);
radeon_surfaces_release(filp, dev_priv);
@@ -3236,6 +3220,14 @@ void radeon_driver_preclose(drm_device_t * dev, DRMFILE filp)
void radeon_driver_lastclose(drm_device_t * dev)
{
+ if (dev->dev_private) {
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+
+ if (dev_priv->sarea_priv &&
+ dev_priv->sarea_priv->pfCurrentPage != 0)
+ radeon_cp_dispatch_flip(dev);
+ }
+
radeon_do_release(dev);
}
diff --git a/shared-core/savage_bci.c b/shared-core/savage_bci.c
index 5632b5c8..9a3ae1f1 100644
--- a/shared-core/savage_bci.c
+++ b/shared-core/savage_bci.c
@@ -710,7 +710,7 @@ static int savage_do_init_bci(drm_device_t *dev, drm_savage_init_t *init)
dev_priv->texture_offset = init->texture_offset;
dev_priv->texture_size = init->texture_size;
- DRM_GETSAREA();
+ dev_priv->sarea = drm_getsarea(dev);
if (!dev_priv->sarea) {
DRM_ERROR("could not find sarea!\n");
savage_do_cleanup_bci(dev);
diff --git a/shared-core/via_map.c b/shared-core/via_map.c
index 83324cfa..037a1c2c 100644
--- a/shared-core/via_map.c
+++ b/shared-core/via_map.c
@@ -32,7 +32,7 @@ static int via_do_init_map(drm_device_t * dev, drm_via_init_t * init)
DRM_DEBUG("%s\n", __FUNCTION__);
- DRM_GETSAREA();
+ dev_priv->sarea = drm_getsarea(dev);
if (!dev_priv->sarea) {
DRM_ERROR("could not find sarea!\n");
dev->dev_private = (void *)dev_priv;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 15:07:50 +0000