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-rw-r--r--shared-core/i915_dma.c78
-rw-r--r--shared-core/i915_drv.h63
-rw-r--r--shared-core/i915_init.c159
3 files changed, 224 insertions, 76 deletions
diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c
index c2a6d863..1c8a0d45 100644
--- a/shared-core/i915_dma.c
+++ b/shared-core/i915_dma.c
@@ -78,7 +78,7 @@ void i915_kernel_lost_context(drm_device_t * dev)
dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
}
-static int i915_dma_cleanup(drm_device_t * dev)
+int i915_dma_cleanup(drm_device_t * dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
/* Make sure interrupts are disabled here because the uninstall ioctl
@@ -853,80 +853,6 @@ static int i915_mmio(DRM_IOCTL_ARGS)
return 0;
}
-int i915_driver_load(drm_device_t *dev, unsigned long flags)
-{
- drm_i915_private_t *dev_priv;
- int ret;
- unsigned long mmiobase, mmiolen;
-
- dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
- if (dev_priv == NULL)
- return DRM_ERR(ENOMEM);
-
- memset(dev_priv, 0, sizeof(drm_i915_private_t));
- dev->dev_private = (void *)dev_priv;
-// dev_priv->flags = flags;
-
- /* i915 has 4 more counters */
- dev->counters += 4;
- dev->types[6] = _DRM_STAT_IRQ;
- dev->types[7] = _DRM_STAT_PRIMARY;
- dev->types[8] = _DRM_STAT_SECONDARY;
- dev->types[9] = _DRM_STAT_DMA;
-
- if (IS_I9XX(dev)) {
- dev_priv->mmiobase = drm_get_resource_start(dev, 0);
- dev_priv->mmiolen = drm_get_resource_len(dev, 0);
- dev_priv->baseaddr = drm_get_resource_start(dev, 2) & 0xff000000;
- } else if (drm_get_resource_start(dev, 1)) {
- dev_priv->mmiobase = drm_get_resource_start(dev, 1);
- dev_priv->mmiolen = drm_get_resource_len(dev, 1);
- dev_priv->baseaddr = drm_get_resource_start(dev, 0) & 0xff000000;
- } else {
- DRM_ERROR("Unable to find MMIO registers or FB\n");
- return -ENODEV;
- }
-
- ret = drm_addmap(dev, dev_priv->mmiobase, dev_priv->mmiolen,
- _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio_map);
- if (ret != 0) {
- DRM_ERROR("Cannot add mapping for MMIO registers\n");
- return ret;
- }
-
- DRM_DEBUG("dev_priv->mmio map is %08X\n", dev_priv->mmio_map);
- intel_modeset_init(dev);
- return 0;
-}
-
-int i915_driver_unload(drm_device_t *dev)
-{
- drm_i915_private_t *dev_priv = dev->dev_private;
-
- intel_modeset_cleanup(dev);
- drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
-
- dev->dev_private = NULL;
- return 0;
-}
-
-void i915_driver_lastclose(drm_device_t * dev)
-{
- drm_i915_private_t *dev_priv = dev->dev_private;
-
- i915_mem_takedown(&(dev_priv->agp_heap));
-
- i915_dma_cleanup(dev);
-
- dev_priv->mmio_map = NULL;
-}
-
-void i915_driver_preclose(drm_device_t * dev, DRMFILE filp)
-{
- drm_i915_private_t *dev_priv = dev->dev_private;
- i915_mem_release(dev, filp, dev_priv->agp_heap);
-}
-
drm_ioctl_desc_t i915_ioctls[] = {
[DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
[DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, DRM_AUTH},
@@ -981,7 +907,7 @@ int i915_driver_firstopen(struct drm_device *dev)
}
}
- DRM_DEBUG("dev_priv->mmio map is %08X\n", dev_priv->mmio_map);
+ DRM_DEBUG("dev_priv->mmio map is %p\n", dev_priv->mmio_map);
return 0;
}
diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h
index 517d0bf6..b1bf0469 100644
--- a/shared-core/i915_drv.h
+++ b/shared-core/i915_drv.h
@@ -134,6 +134,67 @@ typedef struct drm_i915_private {
spinlock_t swaps_lock;
drm_i915_vbl_swap_t vbl_swaps;
unsigned int swaps_pending;
+
+ /* LVDS info */
+ int backlight_duty_cycle; /* restore backlight to this value */
+ bool panel_wants_dither;
+ struct drm_display_mode *panel_fixed_mode;
+
+ /* Register state */
+ u32 saveDSPACNTR;
+ u32 saveDSPBCNTR;
+ u32 savePIPEACONF;
+ u32 savePIPEBCONF;
+ u32 savePIPEASRC;
+ u32 savePIPEBSRC;
+ u32 saveFPA0;
+ u32 saveFPA1;
+ u32 saveDPLL_A;
+ u32 saveDPLL_A_MD;
+ u32 saveHTOTAL_A;
+ u32 saveHBLANK_A;
+ u32 saveHSYNC_A;
+ u32 saveVTOTAL_A;
+ u32 saveVBLANK_A;
+ u32 saveVSYNC_A;
+ u32 saveDSPASTRIDE;
+ u32 saveDSPASIZE;
+ u32 saveDSPAPOS;
+ u32 saveDSPABASE;
+ u32 saveDSPASURF;
+ u32 saveFPB0;
+ u32 saveFPB1;
+ u32 saveDPLL_B;
+ u32 saveDPLL_B_MD;
+ u32 saveHTOTAL_B;
+ u32 saveHBLANK_B;
+ u32 saveHSYNC_B;
+ u32 saveVTOTAL_B;
+ u32 saveVBLANK_B;
+ u32 saveVSYNC_B;
+ u32 saveDSPBSTRIDE;
+ u32 saveDSPBSIZE;
+ u32 saveDSPBPOS;
+ u32 saveDSPBBASE;
+ u32 saveDSPBSURF;
+ u32 saveVCLK_DIVISOR_VGA0;
+ u32 saveVCLK_DIVISOR_VGA1;
+ u32 saveVCLK_POST_DIV;
+ u32 saveVGACNTRL;
+ u32 saveADPA;
+ u32 saveLVDS;
+ u32 saveDVOA;
+ u32 saveDVOB;
+ u32 saveDVOC;
+ u32 savePP_ON;
+ u32 savePP_OFF;
+ u32 savePP_CONTROL;
+ u32 savePP_CYCLE;
+ u32 savePFIT_CONTROL;
+ u32 savePaletteA[256];
+ u32 savePaletteB[256];
+ u32 saveSWF[17];
+ u32 saveBLC_PWM_CTL;
} drm_i915_private_t;
enum intel_chip_family {
@@ -479,6 +540,8 @@ extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
#define PFIT_CONTROL 0x61230
# define PFIT_ENABLE (1 << 31)
+# define PFIT_PIPE_MASK (3 << 29)
+# define PFIT_PIPE_SHIFT 29
# define VERT_INTERP_DISABLE (0 << 10)
# define VERT_INTERP_BILINEAR (1 << 10)
# define VERT_INTERP_MASK (3 << 10)
diff --git a/shared-core/i915_init.c b/shared-core/i915_init.c
new file mode 100644
index 00000000..e454c9fc
--- /dev/null
+++ b/shared-core/i915_init.c
@@ -0,0 +1,159 @@
+#include "drmP.h"
+#include "drm.h"
+#include "drm_sarea.h"
+#include "i915_drm.h"
+#include "i915_drv.h"
+
+int i915_driver_load(drm_device_t *dev, unsigned long flags)
+{
+ drm_i915_private_t *dev_priv;
+ drm_i915_init_t init;
+ int ret;
+
+ dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
+ if (dev_priv == NULL)
+ return DRM_ERR(ENOMEM);
+
+ memset(dev_priv, 0, sizeof(drm_i915_private_t));
+ dev->dev_private = (void *)dev_priv;
+// dev_priv->flags = flags;
+
+ /* i915 has 4 more counters */
+ dev->counters += 4;
+ dev->types[6] = _DRM_STAT_IRQ;
+ dev->types[7] = _DRM_STAT_PRIMARY;
+ dev->types[8] = _DRM_STAT_SECONDARY;
+ dev->types[9] = _DRM_STAT_DMA;
+
+ if (IS_I9XX(dev)) {
+ dev_priv->mmiobase = drm_get_resource_start(dev, 0);
+ dev_priv->mmiolen = drm_get_resource_len(dev, 0);
+ dev_priv->baseaddr = drm_get_resource_start(dev, 2) & 0xff000000;
+ } else if (drm_get_resource_start(dev, 1)) {
+ dev_priv->mmiobase = drm_get_resource_start(dev, 1);
+ dev_priv->mmiolen = drm_get_resource_len(dev, 1);
+ dev_priv->baseaddr = drm_get_resource_start(dev, 0) & 0xff000000;
+ } else {
+ DRM_ERROR("Unable to find MMIO registers\n");
+ return -ENODEV;
+ }
+
+ ret = drm_addmap(dev, dev_priv->mmiobase, dev_priv->mmiolen,
+ _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio_map);
+ if (ret != 0) {
+ DRM_ERROR("Cannot add mapping for MMIO registers\n");
+ return ret;
+ }
+
+
+ ret = drm_setup(dev);
+ if (ret) {
+ DRM_ERROR("drm_setup failed\n");
+ return ret;
+ }
+
+ DRM_GETSAREA();
+ if (!dev_priv->sarea) {
+ DRM_ERROR("can not find sarea!\n");
+ dev->dev_private = (void *)dev_priv;
+ i915_dma_cleanup(dev);
+ return DRM_ERR(EINVAL);
+ }
+
+ /* FIXME: where does the sarea_priv really go? */
+ dev_priv->sarea_priv = kmalloc(sizeof(drm_i915_sarea_t), GFP_KERNEL);
+
+ /* FIXME: need real front buffer offset */
+ dev_priv->sarea_priv->front_handle = 0xa0000000 + 1024*1024;
+
+ drm_bo_driver_init(dev);
+ /* this probably doesn't belong here - TODO */
+ //drm_framebuffer_set_object(dev, dev_priv->sarea_priv->front_handle);
+ intel_modeset_init(dev);
+ drm_set_desired_modes(dev);
+
+ /* FIXME: command ring needs AGP space, do we own it at this point? */
+ dev_priv->ring.Start = 0xa0000000;
+ dev_priv->ring.End = 128*1024;
+ dev_priv->ring.Size = 128*1024;
+ dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
+
+ dev_priv->ring.map.offset = dev_priv->ring.Start;
+ dev_priv->ring.map.size = dev_priv->ring.Size;
+ dev_priv->ring.map.type = 0;
+ dev_priv->ring.map.flags = 0;
+ dev_priv->ring.map.mtrr = 0;
+
+ drm_core_ioremap(&dev_priv->ring.map, dev);
+
+ if (dev_priv->ring.map.handle == NULL) {
+ dev->dev_private = (void *)dev_priv;
+ i915_dma_cleanup(dev);
+ DRM_ERROR("can not ioremap virtual address for"
+ " ring buffer\n");
+ return DRM_ERR(ENOMEM);
+ }
+
+ dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
+ dev_priv->cpp = 4;
+ dev_priv->sarea_priv->pf_current_page = 0;
+
+ /* We are using separate values as placeholders for mechanisms for
+ * private backbuffer/depthbuffer usage.
+ */
+ dev_priv->use_mi_batchbuffer_start = 0;
+
+ /* Allow hardware batchbuffers unless told otherwise.
+ */
+ dev_priv->allow_batchbuffer = 1;
+
+ /* Program Hardware Status Page */
+ dev_priv->status_page_dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE,
+ 0xffffffff);
+
+ if (!dev_priv->status_page_dmah) {
+ dev->dev_private = (void *)dev_priv;
+ i915_dma_cleanup(dev);
+ DRM_ERROR("Can not allocate hardware status page\n");
+ return DRM_ERR(ENOMEM);
+ }
+ dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
+ dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
+
+ memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
+ DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
+
+ I915_WRITE(0x02080, dev_priv->dma_status_page);
+ DRM_DEBUG("Enabled hardware status page\n");
+
+ return 0;
+}
+
+int i915_driver_unload(drm_device_t *dev)
+{
+ drm_i915_private_t *dev_priv = dev->dev_private;
+
+ intel_modeset_cleanup(dev);
+ drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
+
+ dev->dev_private = NULL;
+ return 0;
+}
+
+void i915_driver_lastclose(drm_device_t * dev)
+{
+ drm_i915_private_t *dev_priv = dev->dev_private;
+
+ i915_mem_takedown(&(dev_priv->agp_heap));
+
+ i915_dma_cleanup(dev);
+
+ dev_priv->mmio_map = NULL;
+}
+
+void i915_driver_preclose(drm_device_t * dev, DRMFILE filp)
+{
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ i915_mem_release(dev, filp, dev_priv->agp_heap);
+}
+
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 19:55:48 +0000