diff options
Diffstat (limited to 'shared-core')
| -rw-r--r-- | shared-core/drm.h | 3 | ||||
| -rw-r--r-- | shared-core/drm_pciids.txt | 26 | ||||
| -rw-r--r-- | shared-core/i915_dma.c | 2 | ||||
| -rw-r--r-- | shared-core/i915_drv.h | 7 | ||||
| -rw-r--r-- | shared-core/nouveau_drv.h | 9 | ||||
| -rw-r--r-- | shared-core/nouveau_fifo.c | 339 | ||||
| -rw-r--r-- | shared-core/nouveau_irq.c | 118 | ||||
| -rw-r--r-- | shared-core/nouveau_reg.h | 494 | ||||
| -rw-r--r-- | shared-core/nouveau_state.c | 8 | ||||
| -rw-r--r-- | shared-core/nv04_graph.c | 234 | ||||
| -rw-r--r-- | shared-core/nv10_graph.c | 521 | ||||
| -rw-r--r-- | shared-core/nv20_graph.c | 34 | ||||
| -rw-r--r-- | shared-core/nv30_graph.c | 12 | ||||
| -rw-r--r-- | shared-core/nv40_graph.c | 30 | ||||
| -rw-r--r-- | shared-core/via_dma.c | 134 | ||||
| -rw-r--r-- | shared-core/via_drm.h | 4 | ||||
| -rw-r--r-- | shared-core/via_drv.h | 1 |
17 files changed, 1154 insertions, 822 deletions
diff --git a/shared-core/drm.h b/shared-core/drm.h index 9efb1dc4..0e3b9b89 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -61,6 +61,9 @@ #ifndef __user #define __user #endif +#ifndef __iomem +#define __iomem +#endif #ifdef __GNUC__ # define DEPRECATED __attribute__ ((deprecated)) diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt index 0d2639e1..0fc9775b 100644 --- a/shared-core/drm_pciids.txt +++ b/shared-core/drm_pciids.txt @@ -186,7 +186,7 @@ 0x1002 0x4c51 0 "3D Rage LT Pro" 0x1002 0x4c42 0 "3D Rage LT Pro AGP-133" 0x1002 0x4c44 0 "3D Rage LT Pro AGP-66" -0x1002 0x4759 0 "Rage 3D IICATI 3D RAGE IIC AGP(A12/A13) +0x1002 0x4759 0 "Rage 3D IICATI 3D RAGE IIC AGP(A12/A13)" 0x1002 0x474c 0 "Rage XC" 0x1002 0x474f 0 "Rage XL" 0x1002 0x4752 0 "Rage XL" @@ -266,18 +266,18 @@ [ffb] [i915] -0x8086 0x3577 0 "Intel i830M GMCH" -0x8086 0x2562 0 "Intel i845G GMCH" -0x8086 0x3582 0 "Intel i852GM/i855GM GMCH" -0x8086 0x2572 0 "Intel i865G GMCH" -0x8086 0x2582 0 "Intel i915G" -0x8086 0x2592 0 "Intel i915GM" -0x8086 0x2772 0 "Intel i945G" -0x8086 0x27A2 0 "Intel i945GM" -0x8086 0x2972 0 "Intel i946GZ" -0x8086 0x2982 0 "Intel i965G" -0x8086 0x2992 0 "Intel i965Q" -0x8086 0x29A2 0 "Intel i965G" +0x8086 0x3577 CHIP_I8XX "Intel i830M GMCH" +0x8086 0x2562 CHIP_I8XX "Intel i845G GMCH" +0x8086 0x3582 CHIP_I8XX "Intel i852GM/i855GM GMCH" +0x8086 0x2572 CHIP_I8XX "Intel i865G GMCH" +0x8086 0x2582 CHIP_I9XX|CHIP_I915 "Intel i915G" +0x8086 0x2592 CHIP_I9XX|CHIP_I915 "Intel i915GM" +0x8086 0x2772 CHIP_I9XX|CHIP_I915 "Intel i945G" +0x8086 0x27A2 CHIP_I9XX|CHIP_I915 "Intel i945GM" +0x8086 0x2972 CHIP_I9XX|CHIP_I965 "Intel i946GZ" +0x8086 0x2982 CHIP_I9XX|CHIP_I965 "Intel i965G" +0x8086 0x2992 CHIP_I9XX|CHIP_I965 "Intel i965Q" +0x8086 0x29A2 CHIP_I9XX|CHIP_I965 "Intel i965G" [imagine] 0x105d 0x2309 IMAGINE_128 "Imagine 128" diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index 912fe0b1..9624fac4 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -798,7 +798,7 @@ static int i915_mmio(DRM_IOCTL_ARGS) DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL(mmio, (drm_i915_setparam_t __user *) data, + DRM_COPY_FROM_USER_IOCTL(mmio, (drm_i915_mmio_t __user *) data, sizeof(mmio)); if (mmio.reg >= mmio_table_size) diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index ef9f3638..5a76cb15 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -132,6 +132,13 @@ typedef struct drm_i915_private { unsigned int swaps_pending; } drm_i915_private_t; +enum intel_chip_family { + CHIP_I8XX = 0x01, + CHIP_I9XX = 0x02, + CHIP_I915 = 0x04, + CHIP_I965 = 0x08, +}; + extern drm_ioctl_desc_t i915_ioctls[]; extern int i915_max_ioctl; diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 522a8cf9..63721650 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -91,7 +91,7 @@ struct nouveau_fifo struct nouveau_object *objs; /* XXX dynamic alloc ? */ - uint32_t nv10_pgraph_ctx [340]; + uint32_t pgraph_ctx [340]; }; struct nouveau_config { @@ -104,6 +104,8 @@ struct nouveau_config { typedef struct drm_nouveau_private { /* the card type, takes NV_* as values */ int card_type; + /* exact chipset, derived from NV_PMC_BOOT_0 */ + int chipset; int flags; drm_local_map_t *mmio; @@ -202,6 +204,11 @@ extern void nouveau_irq_preinstall(drm_device_t*); extern void nouveau_irq_postinstall(drm_device_t*); extern void nouveau_irq_uninstall(drm_device_t*); +/* nv04_graph.c */ +extern void nouveau_nv04_context_switch(drm_device_t *dev); +extern int nv04_graph_init(drm_device_t *dev); +extern int nv04_graph_context_create(drm_device_t *dev, int channel); + /* nv10_graph.c */ extern void nouveau_nv10_context_switch(drm_device_t *dev); extern int nv10_graph_init(drm_device_t *dev); diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index e80ba766..7f929c5c 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -82,7 +82,7 @@ static int nouveau_fifo_instmem_configure(drm_device_t *dev) dev_priv->ramht_offset = 0x10000; dev_priv->ramht_bits = 9; dev_priv->ramht_size = (1 << dev_priv->ramht_bits); - NV_WRITE(NV_PFIFO_RAMHT, + NV_WRITE(NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | ((dev_priv->ramht_bits - 9) << 16) | (dev_priv->ramht_offset >> 8) @@ -94,7 +94,7 @@ static int nouveau_fifo_instmem_configure(drm_device_t *dev) /* FIFO runout table (RAMRO) - 512k at 0x11200 */ dev_priv->ramro_offset = 0x11200; dev_priv->ramro_size = 512; - NV_WRITE(NV_PFIFO_RAMRO, dev_priv->ramro_offset>>8); + NV_WRITE(NV03_PFIFO_RAMRO, dev_priv->ramro_offset>>8); DRM_DEBUG("RAMRO offset=0x%x, size=%d\n", dev_priv->ramro_offset, dev_priv->ramro_size); @@ -124,14 +124,14 @@ static int nouveau_fifo_instmem_configure(drm_device_t *dev) case NV_10: dev_priv->ramfc_offset = 0x11400; dev_priv->ramfc_size = nouveau_fifo_number(dev) * nouveau_fifo_ctx_size(dev); - NV_WRITE(NV_PFIFO_RAMFC, (dev_priv->ramfc_offset>>8) | + NV_WRITE(NV03_PFIFO_RAMFC, (dev_priv->ramfc_offset>>8) | (1 << 16) /* 64 Bytes entry*/); break; case NV_04: case NV_03: dev_priv->ramfc_offset = 0x11400; dev_priv->ramfc_size = nouveau_fifo_number(dev) * nouveau_fifo_ctx_size(dev); - NV_WRITE(NV_PFIFO_RAMFC, dev_priv->ramfc_offset>>8); + NV_WRITE(NV03_PFIFO_RAMFC, dev_priv->ramfc_offset>>8); break; } DRM_DEBUG("RAMFC offset=0x%x, size=%d\n", @@ -150,7 +150,7 @@ int nouveau_fifo_init(drm_device_t *dev) drm_nouveau_private_t *dev_priv = dev->dev_private; int ret; - NV_WRITE(NV_PFIFO_CACHES, 0x00000000); + NV_WRITE(NV03_PFIFO_CACHES, 0x00000000); ret = nouveau_fifo_instmem_configure(dev); if (ret) { @@ -163,50 +163,55 @@ int nouveau_fifo_init(drm_device_t *dev) DRM_DEBUG("Setting defaults for remaining PFIFO regs\n"); /* All channels into PIO mode */ - NV_WRITE(NV_PFIFO_MODE, 0x00000000); + NV_WRITE(NV04_PFIFO_MODE, 0x00000000); - NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000000); - NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000); + NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000); + NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000); /* Channel 0 active, PIO mode */ - NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00000000); + NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, 0x00000000); /* PUT and GET to 0 */ - NV_WRITE(NV_PFIFO_CACH1_DMAP, 0x00000000); - NV_WRITE(NV_PFIFO_CACH1_DMAP, 0x00000000); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, 0x00000000); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, 0x00000000); /* No cmdbuf object */ - NV_WRITE(NV_PFIFO_CACH1_DMAI, 0x00000000); - NV_WRITE(NV_PFIFO_CACH0_PSH0, 0x00000000); - NV_WRITE(NV_PFIFO_CACH0_PUL0, 0x00000000); - NV_WRITE(NV_PFIFO_SIZE, 0x0000FFFF); - NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF); - NV_WRITE(NV_PFIFO_CACH0_PUL1, 0x00000001); - NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000); - NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000); - NV_WRITE(NV_PFIFO_CACH1_ENG, 0x00000000); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, 0x00000000); + NV_WRITE(NV03_PFIFO_CACHE0_PUSH0, 0x00000000); + NV_WRITE(NV03_PFIFO_CACHE0_PULL0, 0x00000000); + NV_WRITE(NV04_PFIFO_SIZE, 0x0000FFFF); + NV_WRITE(NV04_PFIFO_CACHE1_HASH, 0x0000FFFF); + NV_WRITE(NV04_PFIFO_CACHE0_PULL1, 0x00000001); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, 0x00000000); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000); + NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, 0x00000000); + + NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 | #ifdef __BIG_ENDIAN - NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES | - NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES | - NV_PFIFO_CACH1_DMAF_MAX_REQS_4 | - NV_PFIFO_CACH1_BIG_ENDIAN); -#else - NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES | - NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES | - NV_PFIFO_CACH1_DMAF_MAX_REQS_4); -#endif - NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0x00000001); - NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000001); - NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001); - NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001); - - NV_WRITE(NV_PGRAPH_CTX_USER, 0x0); - NV_WRITE(NV_PFIFO_DELAY_0, 0xff /* retrycount*/ ); - if (dev_priv->card_type >= NV_40) - NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x00002001); - else - NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10110000); - - NV_WRITE(NV_PFIFO_DMA_TIMESLICE, 0x001fffff); - NV_WRITE(NV_PFIFO_CACHES, 0x00000001); + NV_PFIFO_CACH1_BIG_ENDIAN | +#endif + 0x00000000); + + NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001); + NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001); + NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001); + NV_WRITE(NV04_PFIFO_CACHE1_PULL1, 0x00000001); + + /* FIXME on NV04 */ + if (dev_priv->card_type >= NV_10) { + NV_WRITE(NV10_PGRAPH_CTX_USER, 0x0); + NV_WRITE(NV04_PFIFO_DELAY_0, 0xff /* retrycount*/ ); + if (dev_priv->card_type >= NV_40) + NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x00002001); + else + NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10110000); + } else { + NV_WRITE(NV04_PGRAPH_CTX_USER, 0x0); + NV_WRITE(NV04_PFIFO_DELAY_0, 0xff /* retrycount*/ ); + NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10110000); + } + NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, 0x001fffff); + NV_WRITE(NV03_PFIFO_CACHES, 0x00000001); return 0; } @@ -283,16 +288,14 @@ static void nouveau_nv04_context_init(drm_device_t *dev, RAMFC_WR(DMA_PUT , init->put_base); RAMFC_WR(DMA_GET , init->put_base); RAMFC_WR(DMA_INSTANCE , nouveau_chip_instance_get(dev, cb_obj->instance)); + + RAMFC_WR(DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 | #ifdef __BIG_ENDIAN - RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES | - NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES | - NV_PFIFO_CACH1_DMAF_MAX_REQS_4 | - NV_PFIFO_CACH1_BIG_ENDIAN); -#else - RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES | - NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES | - NV_PFIFO_CACH1_DMAF_MAX_REQS_4); + NV_PFIFO_CACH1_BIG_ENDIAN | #endif + 0x00000000); } #undef RAMFC_WR @@ -318,17 +321,14 @@ static void nouveau_nv10_context_init(drm_device_t *dev, RAMFC_WR(DMA_GET , init->put_base); RAMFC_WR(DMA_INSTANCE , nouveau_chip_instance_get(dev, cb_obj->instance)); + + RAMFC_WR(DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 | #ifdef __BIG_ENDIAN - RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES | - NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES | - NV_PFIFO_CACH1_DMAF_MAX_REQS_4 | - NV_PFIFO_CACH1_BIG_ENDIAN); -#else - - RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES | - NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES | - NV_PFIFO_CACH1_DMAF_MAX_REQS_4); + NV_PFIFO_CACH1_BIG_ENDIAN | #endif + 0x00000000); } static void nouveau_nv30_context_init(drm_device_t *dev, @@ -350,24 +350,23 @@ static void nouveau_nv30_context_init(drm_device_t *dev, RAMFC_WR(DMA_PUT, init->put_base); RAMFC_WR(DMA_GET, init->put_base); - RAMFC_WR(REF_CNT, NV_READ(NV_PFIFO_CACH1_REF_CNT)); + RAMFC_WR(REF_CNT, NV_READ(NV10_PFIFO_CACHE1_REF_CNT)); RAMFC_WR(DMA_INSTANCE, cb_inst); - RAMFC_WR(DMA_STATE, NV_READ(NV_PFIFO_CACH1_DMAS)); - RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_128_BYTES | - NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES | - NV_PFIFO_CACH1_DMAF_MAX_REQS_8 | + RAMFC_WR(DMA_STATE, NV_READ(NV04_PFIFO_CACHE1_DMA_STATE)); + RAMFC_WR(DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 | #ifdef __BIG_ENDIAN NV_PFIFO_CACH1_BIG_ENDIAN | -#else - 0x00000000); #endif + 0x00000000); - RAMFC_WR(ENGINE, NV_READ(NV_PFIFO_CACH1_ENG)); - RAMFC_WR(PULL1_ENGINE, NV_READ(NV_PFIFO_CACH1_PUL1)); - RAMFC_WR(ACQUIRE_VALUE, NV_READ(NV_PFIFO_CACH1_ACQUIRE_VALUE)); - RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP)); - RAMFC_WR(ACQUIRE_TIMEOUT, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMEOUT)); - RAMFC_WR(SEMAPHORE, NV_READ(NV_PFIFO_CACH1_SEMAPHORE)); + RAMFC_WR(ENGINE, NV_READ(NV04_PFIFO_CACHE1_ENGINE)); + RAMFC_WR(PULL1_ENGINE, NV_READ(NV04_PFIFO_CACHE1_PULL1)); + RAMFC_WR(ACQUIRE_VALUE, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE)); + RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP)); + RAMFC_WR(ACQUIRE_TIMEOUT, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT)); + RAMFC_WR(SEMAPHORE, NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE)); RAMFC_WR(DMA_SUBROUTINE, init->put_base); } @@ -378,22 +377,22 @@ static void nouveau_nv10_context_save(drm_device_t *dev) uint32_t fifoctx; int channel; - channel = NV_READ(NV_PFIFO_CACH1_PSH1) & (nouveau_fifo_number(dev)-1); + channel = NV_READ(NV03_PFIFO_CACHE1_PUSH1) & (nouveau_fifo_number(dev)-1); fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*64; - RAMFC_WR(DMA_PUT , NV_READ(NV_PFIFO_CACH1_DMAP)); - RAMFC_WR(DMA_GET , NV_READ(NV_PFIFO_CACH1_DMAG)); - RAMFC_WR(REF_CNT , NV_READ(NV_PFIFO_CACH1_REF_CNT)); - RAMFC_WR(DMA_INSTANCE , NV_READ(NV_PFIFO_CACH1_DMAI)); - RAMFC_WR(DMA_STATE , NV_READ(NV_PFIFO_CACH1_DMAS)); - RAMFC_WR(DMA_FETCH , NV_READ(NV_PFIFO_CACH1_DMAF)); - RAMFC_WR(ENGINE , NV_READ(NV_PFIFO_CACH1_ENG)); - RAMFC_WR(PULL1_ENGINE , NV_READ(NV_PFIFO_CACH1_PUL1)); - RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV_PFIFO_CACH1_ACQUIRE_VALUE)); - RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP)); - RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMEOUT)); - RAMFC_WR(SEMAPHORE , NV_READ(NV_PFIFO_CACH1_SEMAPHORE)); - RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV_PFIFO_CACH1_DMASR)); + RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); + RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); + RAMFC_WR(REF_CNT , NV_READ(NV10_PFIFO_CACHE1_REF_CNT)); + RAMFC_WR(DMA_INSTANCE , NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE)); + RAMFC_WR(DMA_STATE , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE)); + RAMFC_WR(DMA_FETCH , NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH)); + RAMFC_WR(ENGINE , NV_READ(NV04_PFIFO_CACHE1_ENGINE)); + RAMFC_WR(PULL1_ENGINE , NV_READ(NV04_PFIFO_CACHE1_PULL1)); + RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE)); + RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP)); + RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT)); + RAMFC_WR(SEMAPHORE , NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE)); + RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV10_PFIFO_CACHE1_DMA_SUBROUTINE)); } #undef RAMFC_WR @@ -418,9 +417,9 @@ static void nouveau_nv40_context_init(drm_device_t *dev, RAMFC_WR(DMA_PUT , init->put_base); RAMFC_WR(DMA_GET , init->put_base); RAMFC_WR(DMA_INSTANCE , cb_inst); - RAMFC_WR(DMA_FETCH , NV_PFIFO_CACH1_DMAF_TRIG_128_BYTES | - NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES | - NV_PFIFO_CACH1_DMAF_MAX_REQS_8 | + RAMFC_WR(DMA_FETCH , NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 | #ifdef __BIG_ENDIAN NV_PFIFO_CACH1_BIG_ENDIAN | #endif @@ -436,25 +435,25 @@ static void nouveau_nv40_context_save(drm_device_t *dev) uint32_t fifoctx; int channel; - channel = NV_READ(NV_PFIFO_CACH1_PSH1) & (nouveau_fifo_number(dev)-1); + channel = NV_READ(NV03_PFIFO_CACHE1_PUSH1) & (nouveau_fifo_number(dev)-1); fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*128; - RAMFC_WR(DMA_PUT , NV_READ(NV_PFIFO_CACH1_DMAP)); - RAMFC_WR(DMA_GET , NV_READ(NV_PFIFO_CACH1_DMAG)); - RAMFC_WR(REF_CNT , NV_READ(NV_PFIFO_CACH1_REF_CNT)); - RAMFC_WR(DMA_INSTANCE , NV_READ(NV_PFIFO_CACH1_DMAI)); - RAMFC_WR(DMA_DCOUNT , NV_READ(NV_PFIFO_CACH1_DMA_DCOUNT)); - RAMFC_WR(DMA_STATE , NV_READ(NV_PFIFO_CACH1_DMAS)); - RAMFC_WR(DMA_FETCH , NV_READ(NV_PFIFO_CACH1_DMAF)); - RAMFC_WR(ENGINE , NV_READ(NV_PFIFO_CACH1_ENG)); - RAMFC_WR(PULL1_ENGINE , NV_READ(NV_PFIFO_CACH1_PUL1)); - RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV_PFIFO_CACH1_ACQUIRE_VALUE)); - RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP)); - RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMEOUT)); - RAMFC_WR(SEMAPHORE , NV_READ(NV_PFIFO_CACH1_SEMAPHORE)); - RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV_PFIFO_CACH1_DMAG)); + RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); + RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); + RAMFC_WR(REF_CNT , NV_READ(NV10_PFIFO_CACHE1_REF_CNT)); + RAMFC_WR(DMA_INSTANCE , NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE)); + RAMFC_WR(DMA_DCOUNT , NV_READ(NV10_PFIFO_CACHE1_DMA_DCOUNT)); + RAMFC_WR(DMA_STATE , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE)); + RAMFC_WR(DMA_FETCH , NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH)); + RAMFC_WR(ENGINE , NV_READ(NV04_PFIFO_CACHE1_ENGINE)); + RAMFC_WR(PULL1_ENGINE , NV_READ(NV04_PFIFO_CACHE1_PULL1)); + RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE)); + RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP)); + RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT)); + RAMFC_WR(SEMAPHORE , NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE)); + RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); RAMFC_WR(GRCTX_INSTANCE , NV_READ(NV40_PFIFO_GRCTX_INSTANCE)); - RAMFC_WR(DMA_TIMESLICE , NV_READ(NV_PFIFO_DMA_TIMESLICE) & 0x1FFFF); + RAMFC_WR(DMA_TIMESLICE , NV_READ(NV04_PFIFO_DMA_TIMESLICE) & 0x1FFFF); RAMFC_WR(UNK_40 , NV_READ(NV40_PFIFO_UNK32E4)); } #undef RAMFC_WR @@ -475,25 +474,28 @@ nouveau_fifo_context_restore(drm_device_t *dev, int channel) // FIXME check if we need to refill the time quota with something like NV_WRITE(0x204C, 0x0003FFFF); if (dev_priv->card_type >= NV_40) - NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00010000|channel); + NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, 0x00010000|channel); else - NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00000100|channel); - - NV_WRITE(NV_PFIFO_CACH1_DMAP, 0 /*RAMFC_DMA_PUT*/); - NV_WRITE(NV_PFIFO_CACH1_DMAG, 0 /*RAMFC_DMA_GET*/); - NV_WRITE(NV_PFIFO_CACH1_DMAI, cb_inst); - NV_WRITE(NV_PFIFO_SIZE , 0x0000FFFF); - NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF); - - NV_WRITE(NV_PFIFO_CACH0_PUL1, 0x00000001); - NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000); - NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000); - NV_WRITE(NV_PFIFO_CACH1_ENG, 0x00000000); + NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, 0x00000100|channel); + + NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, 0 /*RAMFC_DMA_PUT*/); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, 0 /*RAMFC_DMA_GET*/); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, cb_inst); + NV_WRITE(NV04_PFIFO_SIZE , 0x0000FFFF); + NV_WRITE(NV04_PFIFO_CACHE1_HASH, 0x0000FFFF); + + NV_WRITE(NV04_PFIFO_CACHE0_PULL1, 0x00000001); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, 0x00000000); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000); + NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, 0x00000000); + + NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 | #ifdef __BIG_ENDIAN - NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN); -#else - NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4); + NV_PFIFO_CACH1_BIG_ENDIAN | #endif + 0x00000000); } /* allocates and initializes a fifo for user space consumption */ @@ -537,42 +539,53 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init, nouveau_wait_for_idle(dev); /* disable the fifo caches */ - NV_WRITE(NV_PFIFO_CACHES, 0x00000000); - NV_WRITE(NV_PFIFO_CACH1_DMAPSH, NV_READ(NV_PFIFO_CACH1_DMAPSH)&(~0x1)); - NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000000); - NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000); + NV_WRITE(NV03_PFIFO_CACHES, 0x00000000); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH)&(~0x1)); + NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000); + NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000); /* Construct inital RAMFC for new channel */ - if (dev_priv->card_type < NV_10) { - nouveau_nv04_context_init(dev, init); - } else if (dev_priv->card_type < NV_20) { - nv10_graph_context_create(dev, init->channel); - nouveau_nv10_context_init(dev, init); - } else if (dev_priv->card_type < NV_30) { - ret = nv20_graph_context_create(dev, init->channel); - if (ret) { - nouveau_fifo_free(dev, init->channel); - return ret; - } - nouveau_nv10_context_init(dev, init); - } else if (dev_priv->card_type < NV_40) { - ret = nv30_graph_context_create(dev, init->channel); - if (ret) { - nouveau_fifo_free(dev, init->channel); - return ret; - } - nouveau_nv30_context_init(dev, init); - } else { - ret = nv40_graph_context_create(dev, init->channel); - if (ret) { - nouveau_fifo_free(dev, init->channel); - return ret; - } - nouveau_nv40_context_init(dev, init); + switch(dev_priv->card_type) + { + case NV_04: + case NV_05: + nv04_graph_context_create(dev, init->channel); + nouveau_nv04_context_init(dev, init); + break; + case NV_10: + nv10_graph_context_create(dev, init->channel); + nouveau_nv10_context_init(dev, init); + break; + case NV_20: + ret = nv20_graph_context_create(dev, init->channel); + if (ret) { + nouveau_fifo_free(dev, init->channel); + return ret; + } + nouveau_nv10_context_init(dev, init); + break; + case NV_30: + ret = nv30_graph_context_create(dev, init->channel); + if (ret) { + nouveau_fifo_free(dev, init->channel); + return ret; + } + nouveau_nv30_context_init(dev, init); + break; + case NV_40: + case NV_44: + case NV_50: + ret = nv40_graph_context_create(dev, init->channel); + if (ret) { + nouveau_fifo_free(dev, init->channel); + return ret; + } + nouveau_nv40_context_init(dev, init); + break; } /* enable the fifo dma operation */ - NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)|(1<<init->channel)); + NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<<init->channel)); /* setup channel's default get/put values */ NV_WRITE(NV03_FIFO_REGS_DMAPUT(init->channel), init->put_base); @@ -592,7 +605,7 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init, chan->ramin_grctx); /* see comments in nv40_graph_context_restore() */ - NV_WRITE(NV_PGRAPH_CHANNEL_CTX_SIZE, inst); + NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, inst); if (dev_priv->card_type >= NV_40) { NV_WRITE(0x40032C, inst | 0x01000000); NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE, inst); @@ -600,13 +613,13 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init, } } - NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0x00000001); - NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000001); - NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001); - NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001); + NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001); + NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001); + NV_WRITE(NV04_PFIFO_CACHE1_PULL1, 0x00000001); /* reenable the fifo caches */ - NV_WRITE(NV_PFIFO_CACHES, 0x00000001); + NV_WRITE(NV03_PFIFO_CACHES, 0x00000001); /* make the fifo available to user space */ /* first, the fifo control regs */ @@ -640,9 +653,9 @@ void nouveau_fifo_free(drm_device_t* dev,int n) DRM_INFO("%s: freeing fifo %d\n", __func__, n); /* disable the fifo caches */ - NV_WRITE(NV_PFIFO_CACHES, 0x00000000); + NV_WRITE(NV03_PFIFO_CACHES, 0x00000000); - NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)&~(1<<n)); + NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)&~(1<<n)); // FIXME XXX needs more code /* Clean RAMFC */ @@ -663,7 +676,7 @@ void nouveau_fifo_free(drm_device_t* dev,int n) } /* reenable the fifo caches */ - NV_WRITE(NV_PFIFO_CACHES, 0x00000001); + NV_WRITE(NV03_PFIFO_CACHES, 0x00000001); /* Deallocate command buffer, and dma object */ nouveau_mem_free(dev, dev_priv->fifos[n].cmdbuf_mem); @@ -741,5 +754,3 @@ drm_ioctl_desc_t nouveau_ioctls[] = { }; int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls); - - diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index ac88b684..51d4bae1 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -43,14 +43,14 @@ void nouveau_irq_preinstall(drm_device_t *dev) DRM_DEBUG("IRQ: preinst\n"); /* Disable/Clear PFIFO interrupts */ - NV_WRITE(NV_PFIFO_INTEN, 0); - NV_WRITE(NV_PFIFO_INTSTAT, 0xFFFFFFFF); + NV_WRITE(NV03_PFIFO_INTR_EN_0, 0); + NV_WRITE(NV03_PMC_INTR_0, 0xFFFFFFFF); /* Disable/Clear PGRAPH interrupts */ if (dev_priv->card_type<NV_40) - NV_WRITE(NV04_PGRAPH_INTEN, 0); + NV_WRITE(NV03_PGRAPH_INTR_EN, 0); else - NV_WRITE(NV40_PGRAPH_INTEN, 0); - NV_WRITE(NV_PGRAPH_INTSTAT, 0xFFFFFFFF); + NV_WRITE(NV40_PGRAPH_INTR_EN, 0); + NV_WRITE(NV03_PGRAPH_INTR, 0xFFFFFFFF); #if 0 /* Disable/Clear CRTC0/1 interrupts */ NV_WRITE(NV_CRTC0_INTEN, 0); @@ -59,7 +59,7 @@ void nouveau_irq_preinstall(drm_device_t *dev) NV_WRITE(NV_CRTC1_INTSTAT, NV_CRTC_INTR_VBLANK); #endif /* Master disable */ - NV_WRITE(NV_PMC_INTEN, 0); + NV_WRITE(NV03_PMC_INTR_EN_0, 0); } void nouveau_irq_postinstall(drm_device_t *dev) @@ -69,7 +69,7 @@ void nouveau_irq_postinstall(drm_device_t *dev) DRM_DEBUG("IRQ: postinst\n"); /* Enable PFIFO error reporting */ - NV_WRITE(NV_PFIFO_INTEN , + NV_WRITE(NV03_PFIFO_INTR_EN_0 , NV_PFIFO_INTR_CACHE_ERROR | NV_PFIFO_INTR_RUNOUT | NV_PFIFO_INTR_RUNOUT_OVERFLOW | @@ -78,11 +78,11 @@ void nouveau_irq_postinstall(drm_device_t *dev) NV_PFIFO_INTR_SEMAPHORE | NV_PFIFO_INTR_ACQUIRE_TIMEOUT ); - NV_WRITE(NV_PFIFO_INTSTAT, 0xFFFFFFFF); + NV_WRITE(NV03_PMC_INTR_0, 0xFFFFFFFF); /* Enable PGRAPH interrupts */ if (dev_priv->card_type<NV_40) - NV_WRITE(NV04_PGRAPH_INTEN, + NV_WRITE(NV03_PGRAPH_INTR_EN, NV_PGRAPH_INTR_NOTIFY | NV_PGRAPH_INTR_MISSING_HW | NV_PGRAPH_INTR_CONTEXT_SWITCH | @@ -90,14 +90,14 @@ void nouveau_irq_postinstall(drm_device_t *dev) NV_PGRAPH_INTR_ERROR ); else - NV_WRITE(NV40_PGRAPH_INTEN, + NV_WRITE(NV40_PGRAPH_INTR_EN, NV_PGRAPH_INTR_NOTIFY | NV_PGRAPH_INTR_MISSING_HW | NV_PGRAPH_INTR_CONTEXT_SWITCH | NV_PGRAPH_INTR_BUFFER_NOTIFY | NV_PGRAPH_INTR_ERROR ); - NV_WRITE(NV_PGRAPH_INTSTAT, 0xFFFFFFFF); + NV_WRITE(NV03_PGRAPH_INTR, 0xFFFFFFFF); #if 0 /* Enable CRTC0/1 interrupts */ @@ -106,7 +106,7 @@ void nouveau_irq_postinstall(drm_device_t *dev) #endif /* Master enable */ - NV_WRITE(NV_PMC_INTEN, NV_PMC_INTEN_MASTER_ENABLE); + NV_WRITE(NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE); } void nouveau_irq_uninstall(drm_device_t *dev) @@ -116,19 +116,19 @@ void nouveau_irq_uninstall(drm_device_t *dev) DRM_DEBUG("IRQ: uninst\n"); /* Disable PFIFO interrupts */ - NV_WRITE(NV_PFIFO_INTEN, 0); + NV_WRITE(NV03_PFIFO_INTR_EN_0, 0); /* Disable PGRAPH interrupts */ if (dev_priv->card_type<NV_40) - NV_WRITE(NV04_PGRAPH_INTEN, 0); + NV_WRITE(NV03_PGRAPH_INTR_EN, 0); else - NV_WRITE(NV40_PGRAPH_INTEN, 0); + NV_WRITE(NV40_PGRAPH_INTR_EN, 0); #if 0 /* Disable CRTC0/1 interrupts */ NV_WRITE(NV_CRTC0_INTEN, 0); NV_WRITE(NV_CRTC1_INTEN, 0); #endif /* Master disable */ - NV_WRITE(NV_PMC_INTEN, 0); + NV_WRITE(NV03_PMC_INTR_EN_0, 0); } static void nouveau_fifo_irq_handler(drm_device_t *dev) @@ -136,12 +136,12 @@ static void nouveau_fifo_irq_handler(drm_device_t *dev) uint32_t status, chmode, chstat, channel; drm_nouveau_private_t *dev_priv = dev->dev_private; - status = NV_READ(NV_PFIFO_INTSTAT); + status = NV_READ(NV03_PMC_INTR_0); if (!status) return; - chmode = NV_READ(NV_PFIFO_MODE); - chstat = NV_READ(NV_PFIFO_DMA); - channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1); + chmode = NV_READ(NV04_PFIFO_MODE); + chstat = NV_READ(NV04_PFIFO_DMA); + channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); DRM_DEBUG("NV: PFIFO interrupt! Channel=%d, INTSTAT=0x%08x/MODE=0x%08x/PEND=0x%08x\n", channel, status, chmode, chstat); @@ -150,14 +150,14 @@ static void nouveau_fifo_irq_handler(drm_device_t *dev) DRM_ERROR("NV: PFIFO error interrupt\n"); - c1get = NV_READ(NV_PFIFO_CACH1_GET) >> 2; + c1get = NV_READ(NV03_PFIFO_CACHE1_GET) >> 2; if (dev_priv->card_type < NV_40) { /* Untested, so it may not work.. */ - c1method = NV_READ(NV_PFIFO_CACH1_METHOD(c1get)); - c1data = NV_READ(NV_PFIFO_CACH1_DATA(c1get)); + c1method = NV_READ(NV04_PFIFO_CACHE1_METHOD(c1get)); + c1data = NV_READ(NV04_PFIFO_CACHE1_DATA(c1get)); } else { - c1method = NV_READ(NV40_PFIFO_CACH1_METHOD(c1get)); - c1data = NV_READ(NV40_PFIFO_CACH1_DATA(c1get)); + c1method = NV_READ(NV40_PFIFO_CACHE1_METHOD(c1get)); + c1data = NV_READ(NV40_PFIFO_CACHE1_DATA(c1get)); } DRM_ERROR("NV: Channel %d/%d - Method 0x%04x, Data 0x%08x\n", @@ -166,40 +166,41 @@ static void nouveau_fifo_irq_handler(drm_device_t *dev) ); status &= ~NV_PFIFO_INTR_CACHE_ERROR; - NV_WRITE(NV_PFIFO_INTSTAT, NV_PFIFO_INTR_CACHE_ERROR); + NV_WRITE(NV03_PMC_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); } if (status & NV_PFIFO_INTR_DMA_PUSHER) { DRM_INFO("NV: PFIFO DMA pusher interrupt\n"); status &= ~NV_PFIFO_INTR_DMA_PUSHER; - NV_WRITE(NV_PFIFO_INTSTAT, NV_PFIFO_INTR_DMA_PUSHER); + NV_WRITE(NV03_PMC_INTR_0, NV_PFIFO_INTR_DMA_PUSHER); - NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000); - if (NV_READ(NV_PFIFO_CACH1_DMAP)!=NV_READ(NV_PFIFO_CACH1_DMAG)) + NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000); + if (NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)!=NV_READ(NV04_PFIFO_CACHE1_DMA_GET)) { - uint32_t getval=NV_READ(NV_PFIFO_CACH1_DMAG)+4; - NV_WRITE(NV_PFIFO_CACH1_DMAG,getval); + uint32_t getval=NV_READ(NV04_PFIFO_CACHE1_DMA_GET)+4; + NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET,getval); } } if (status) { DRM_INFO("NV: unknown PFIFO interrupt. status=0x%08x\n", status); - NV_WRITE(NV_PFIFO_INTSTAT, status); + NV_WRITE(NV03_PMC_INTR_0, status); } - NV_WRITE(NV_PMC_INTSTAT, NV_PMC_INTSTAT_PFIFO_PENDING); + NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING); } +#if 0 static void nouveau_nv04_context_switch(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = dev->dev_private; uint32_t channel,i; uint32_t max=0; - NV_WRITE(NV_PGRAPH_FIFO,0x0); - channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1); - //DRM_INFO("raw PFIFO_CACH1_PHS1 reg is %x\n",NV_READ(NV_PFIFO_CACH1_PSH1)); + NV_WRITE(NV04_PGRAPH_FIFO,0x0); + channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); + //DRM_INFO("raw PFIFO_CACH1_PHS1 reg is %x\n",NV_READ(NV03_PFIFO_CACHE1_PUSH1)); //DRM_INFO("currently on channel %d\n",channel); for (i=0;i<nouveau_fifo_number(dev);i++) if ((dev_priv->fifos[i].used)&&(i!=channel)) { @@ -208,13 +209,13 @@ static void nouveau_nv04_context_switch(drm_device_t *dev) //get=NV_READ(dev_priv->ramfc_offset+4+i*32); put=NV_READ(NV03_FIFO_REGS_DMAPUT(i)); get=NV_READ(NV03_FIFO_REGS_DMAGET(i)); - pending=NV_READ(NV_PFIFO_DMA); + pending=NV_READ(NV04_PFIFO_DMA); //DRM_INFO("Channel %d (put/get %x/%x)\n",i,put,get); /* mark all pending channels as such */ if ((put!=get)&!(pending&(1<<i))) { pending|=(1<<i); - NV_WRITE(NV_PFIFO_DMA,pending); + NV_WRITE(NV04_PFIFO_DMA,pending); } max++; } @@ -222,27 +223,28 @@ static void nouveau_nv04_context_switch(drm_device_t *dev) #if 1 /* 2-channel commute */ - // NV_WRITE(NV_PFIFO_CACH1_PSH1,channel|0x100); + // NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,channel|0x100); if (channel==0) channel=1; else channel=0; // dev_priv->cur_fifo=channel; - NV_WRITE(0x2050,channel|0x100); + NV_WRITE(NV04_PFIFO_NEXT_CHANNEL,channel|0x100); #endif - //NV_WRITE(NV_PFIFO_CACH1_PSH1,max|0x100); + //NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,max|0x100); //NV_WRITE(0x2050,max|0x100); - NV_WRITE(NV_PGRAPH_FIFO,0x1); + NV_WRITE(NV04_PGRAPH_FIFO,0x1); } +#endif static void nouveau_pgraph_irq_handler(drm_device_t *dev) { uint32_t status; drm_nouveau_private_t *dev_priv = dev->dev_private; - status = NV_READ(NV_PGRAPH_INTSTAT); + status = NV_READ(NV03_PGRAPH_INTR); if (!status) return; @@ -259,7 +261,7 @@ static void nouveau_pgraph_irq_handler(drm_device_t *dev) DRM_DEBUG("instance:0x%08x\tnotify:0x%08x\n", nsource, nstatus); status &= ~NV_PGRAPH_INTR_NOTIFY; - NV_WRITE(NV_PGRAPH_INTSTAT, NV_PGRAPH_INTR_NOTIFY); + NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY); } if (status & NV_PGRAPH_INTR_BUFFER_NOTIFY) { @@ -275,14 +277,14 @@ static void nouveau_pgraph_irq_handler(drm_device_t *dev) DRM_DEBUG("instance:0x%08x\tnotify:0x%08x\n", instance, notify); status &= ~NV_PGRAPH_INTR_BUFFER_NOTIFY; - NV_WRITE(NV_PGRAPH_INTSTAT, NV_PGRAPH_INTR_BUFFER_NOTIFY); + NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_BUFFER_NOTIFY); } if (status & NV_PGRAPH_INTR_MISSING_HW) { DRM_ERROR("NV: PGRAPH missing hw interrupt\n"); status &= ~NV_PGRAPH_INTR_MISSING_HW; - NV_WRITE(NV_PGRAPH_INTSTAT, NV_PGRAPH_INTR_MISSING_HW); + NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_MISSING_HW); } if (status & NV_PGRAPH_INTR_ERROR) { @@ -314,11 +316,11 @@ static void nouveau_pgraph_irq_handler(drm_device_t *dev) ); status &= ~NV_PGRAPH_INTR_ERROR; - NV_WRITE(NV_PGRAPH_INTSTAT, NV_PGRAPH_INTR_ERROR); + NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_ERROR); } if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) { - uint32_t channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1); + uint32_t channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); DRM_INFO("NV: PGRAPH context switch interrupt channel %x\n",channel); switch(dev_priv->card_type) { @@ -339,15 +341,15 @@ static void nouveau_pgraph_irq_handler(drm_device_t *dev) } status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; - NV_WRITE(NV_PGRAPH_INTSTAT, NV_PGRAPH_INTR_CONTEXT_SWITCH); + NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH); } if (status) { DRM_INFO("NV: Unknown PGRAPH interrupt! STAT=0x%08x\n", status); - NV_WRITE(NV_PGRAPH_INTSTAT, status); + NV_WRITE(NV03_PGRAPH_INTR, status); } - NV_WRITE(NV_PMC_INTSTAT, NV_PMC_INTSTAT_PGRAPH_PENDING); + NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING); } static void nouveau_crtc_irq_handler(drm_device_t *dev, int crtc) @@ -368,23 +370,23 @@ irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS) drm_nouveau_private_t *dev_priv = dev->dev_private; uint32_t status; - status = NV_READ(NV_PMC_INTSTAT); + status = NV_READ(NV03_PMC_INTR_0); if (!status) return IRQ_NONE; DRM_DEBUG("PMC INTSTAT: 0x%08x\n", status); - if (status & NV_PMC_INTSTAT_PFIFO_PENDING) { + if (status & NV_PMC_INTR_0_PFIFO_PENDING) { nouveau_fifo_irq_handler(dev); - status &= ~NV_PMC_INTSTAT_PFIFO_PENDING; + status &= ~NV_PMC_INTR_0_PFIFO_PENDING; } - if (status & NV_PMC_INTSTAT_PGRAPH_PENDING) { + if (status & NV_PMC_INTR_0_PGRAPH_PENDING) { nouveau_pgraph_irq_handler(dev); - status &= ~NV_PMC_INTSTAT_PGRAPH_PENDING; + status &= ~NV_PMC_INTR_0_PGRAPH_PENDING; } - if (status & NV_PMC_INTSTAT_CRTCn_PENDING) { + if (status & NV_PMC_INTR_0_CRTCn_PENDING) { nouveau_crtc_irq_handler(dev, (status>>24)&3); - status &= ~NV_PMC_INTSTAT_CRTCn_PENDING; + status &= ~NV_PMC_INTR_0_CRTCn_PENDING; } if (status) diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index 543be694..966600cf 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -45,131 +45,200 @@ # define NV03_FIFO_REGS_DMAPUT(i) (NV03_FIFO_REGS(i)+0x40) # define NV03_FIFO_REGS_DMAGET(i) (NV03_FIFO_REGS(i)+0x44) -#define NV_PMC_BOOT_0 0x00000000 -#define NV_PMC_INTSTAT 0x00000100 -# define NV_PMC_INTSTAT_PFIFO_PENDING (1<< 8) -# define NV_PMC_INTSTAT_PGRAPH_PENDING (1<<12) -# define NV_PMC_INTSTAT_CRTC0_PENDING (1<<24) -# define NV_PMC_INTSTAT_CRTC1_PENDING (1<<25) -# define NV_PMC_INTSTAT_CRTCn_PENDING (3<<24) -#define NV_PMC_INTEN 0x00000140 -# define NV_PMC_INTEN_MASTER_ENABLE (1<< 0) +#define NV03_PMC_BOOT_0 0x00000000 +#define NV03_PMC_INTR_0 0x00000100 +# define NV_PMC_INTR_0_PFIFO_PENDING (1<< 8) +# define NV_PMC_INTR_0_PGRAPH_PENDING (1<<12) +# define NV_PMC_INTR_0_CRTC0_PENDING (1<<24) +# define NV_PMC_INTR_0_CRTC1_PENDING (1<<25) +# define NV_PMC_INTR_0_CRTCn_PENDING (3<<24) +#define NV03_PMC_INTR_EN_0 0x00000140 +# define NV_PMC_INTR_EN_0_MASTER_ENABLE (1<< 0) -#define NV_PGRAPH_DEBUG_4 0x00400090 -#define NV_PGRAPH_INTSTAT 0x00400100 -#define NV04_PGRAPH_INTEN 0x00400140 -#define NV40_PGRAPH_INTEN 0x0040013C +#define NV10_PGRAPH_DEBUG_4 0x00400090 +#define NV03_PGRAPH_INTR 0x00400100 +#define NV03_PGRAPH_INTR_EN 0x00400140 +#define NV40_PGRAPH_INTR_EN 0x0040013C # define NV_PGRAPH_INTR_NOTIFY (1<< 0) # define NV_PGRAPH_INTR_MISSING_HW (1<< 4) # define NV_PGRAPH_INTR_CONTEXT_SWITCH (1<<12) # define NV_PGRAPH_INTR_BUFFER_NOTIFY (1<<16) # define NV_PGRAPH_INTR_ERROR (1<<20) -#define NV_PGRAPH_CTX_CONTROL 0x00400144 -#define NV_PGRAPH_NV40_UNK220 0x00400220 -# define NV_PGRAPH_NV40_UNK220_FB_INSTANCE -#define NV_PGRAPH_CTX_USER 0x00400148 -#define NV_PGRAPH_CTX_SWITCH1 0x0040014C -#define NV_PGRAPH_CTX_SWITCH2 0x00400150 -#define NV_PGRAPH_CTX_SWITCH3 0x00400154 -#define NV_PGRAPH_CTX_SWITCH4 0x00400158 -#define NV_PGRAPH_CTX_SWITCH5 0x0040015C -#define NV_PGRAPH_X_MISC 0x00400500 -#define NV_PGRAPH_Y_MISC 0x00400504 -#define NV_PGRAPH_VALID1 0x00400508 -#define NV_PGRAPH_SOURCE_COLOR 0x0040050C -#define NV_PGRAPH_MISC24_0 0x00400510 -#define NV_PGRAPH_XY_LOGIC_MISC0 0x00400514 -#define NV_PGRAPH_XY_LOGIC_MISC1 0x00400518 -#define NV_PGRAPH_XY_LOGIC_MISC2 0x0040051C -#define NV_PGRAPH_XY_LOGIC_MISC3 0x00400520 -#define NV_PGRAPH_CLIPX_0 0x00400524 -#define NV_PGRAPH_CLIPX_1 0x00400528 -#define NV_PGRAPH_CLIPY_0 0x0040052C -#define NV_PGRAPH_CLIPY_1 0x00400530 -#define NV_PGRAPH_ABS_ICLIP_XMAX 0x00400534 -#define NV_PGRAPH_ABS_ICLIP_YMAX 0x00400538 -#define NV_PGRAPH_ABS_UCLIP_XMIN 0x0040053C -#define NV_PGRAPH_ABS_UCLIP_YMIN 0x00400540 -#define NV_PGRAPH_ABS_UCLIP_XMAX 0x00400544 -#define NV_PGRAPH_ABS_UCLIP_YMAX 0x00400548 -#define NV_PGRAPH_ABS_UCLIPA_XMIN 0x00400560 -#define NV_PGRAPH_ABS_UCLIPA_YMIN 0x00400564 -#define NV_PGRAPH_ABS_UCLIPA_XMAX 0x00400568 -#define NV_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C -#define NV_PGRAPH_MISC24_1 0x00400570 -#define NV_PGRAPH_MISC24_2 0x00400574 -#define NV_PGRAPH_VALID2 0x00400578 -#define NV_PGRAPH_PASSTHRU_0 0x0040057C -#define NV_PGRAPH_PASSTHRU_1 0x00400580 -#define NV_PGRAPH_PASSTHRU_2 0x00400584 -#define NV_PGRAPH_DIMX_TEXTURE 0x00400588 -#define NV_PGRAPH_WDIMX_TEXTURE 0x0040058C -#define NV_PGRAPH_MONO_COLOR0 0x00400600 -#define NV_PGRAPH_ROP3 0x00400604 -#define NV_PGRAPH_BETA_AND 0x00400608 -#define NV_PGRAPH_BETA_PREMULT 0x0040060C -#define NV_PGRAPH_BOFFSET0 0x00400640 -#define NV_PGRAPH_BOFFSET1 0x00400644 -#define NV_PGRAPH_BOFFSET2 0x00400648 -#define NV_PGRAPH_BOFFSET3 0x0040064C -#define NV_PGRAPH_BOFFSET4 0x00400650 -#define NV_PGRAPH_BOFFSET5 0x00400654 -#define NV_PGRAPH_BBASE0 0x00400658 -#define NV_PGRAPH_BBASE1 0x0040065C -#define NV_PGRAPH_BBASE2 0x00400660 -#define NV_PGRAPH_BBASE3 0x00400664 -#define NV_PGRAPH_BBASE4 0x00400668 -#define NV_PGRAPH_BBASE5 0x0040066C -#define NV_PGRAPH_BPITCH0 0x00400670 -#define NV_PGRAPH_BPITCH1 0x00400674 -#define NV_PGRAPH_BPITCH2 0x00400678 -#define NV_PGRAPH_BPITCH3 0x0040067C -#define NV_PGRAPH_BPITCH4 0x00400680 -#define NV_PGRAPH_BLIMIT0 0x00400684 -#define NV_PGRAPH_BLIMIT1 0x00400688 -#define NV_PGRAPH_BLIMIT2 0x0040068C -#define NV_PGRAPH_BLIMIT3 0x00400690 -#define NV_PGRAPH_BLIMIT4 0x00400694 -#define NV_PGRAPH_BLIMIT5 0x00400698 -#define NV_PGRAPH_BSWIZZLE2 0x0040069C -#define NV_PGRAPH_BSWIZZLE5 0x004006A0 -#define NV_PGRAPH_SURFACE 0x00400710 -#define NV_PGRAPH_STATE 0x00400714 -#define NV_PGRAPH_NOTIFY 0x00400718 +#define NV10_PGRAPH_CTX_CONTROL 0x00400144 +#define NV10_PGRAPH_CTX_USER 0x00400148 +#define NV10_PGRAPH_CTX_SWITCH1 0x0040014C +#define NV10_PGRAPH_CTX_SWITCH2 0x00400150 +#define NV10_PGRAPH_CTX_SWITCH3 0x00400154 +#define NV10_PGRAPH_CTX_SWITCH4 0x00400158 +#define NV10_PGRAPH_CTX_SWITCH5 0x0040015C +#define NV04_PGRAPH_CTX_SWITCH1 0x00400160 +#define NV10_PGRAPH_CTX_CACHE1 0x00400160 +#define NV04_PGRAPH_CTX_SWITCH2 0x00400164 +#define NV04_PGRAPH_CTX_SWITCH3 0x00400168 +#define NV04_PGRAPH_CTX_SWITCH4 0x0040016C +#define NV04_PGRAPH_CTX_CONTROL 0x00400170 +#define NV04_PGRAPH_CTX_USER 0x00400174 +#define NV04_PGRAPH_CTX_CACHE1 0x00400180 +#define NV10_PGRAPH_CTX_CACHE2 0x00400180 +#define NV03_PGRAPH_CTX_CONTROL 0x00400190 +#define NV03_PGRAPH_CTX_USER 0x00400194 +#define NV04_PGRAPH_CTX_CACHE2 0x004001A0 +#define NV10_PGRAPH_CTX_CACHE3 0x004001A0 +#define NV04_PGRAPH_CTX_CACHE3 0x004001C0 +#define NV10_PGRAPH_CTX_CACHE4 0x004001C0 +#define NV04_PGRAPH_CTX_CACHE4 0x004001E0 +#define NV10_PGRAPH_CTX_CACHE5 0x004001E0 +#define NV40_PGRAPH_UNK220 0x00400220 +# define NV40_PGRAPH_UNK220_FB_INSTANCE 0xFFFFFFFF +#define NV03_PGRAPH_ABS_X_RAM 0x00400400 +#define NV03_PGRAPH_ABS_Y_RAM 0x00400480 +#define NV03_PGRAPH_X_MISC 0x00400500 +#define NV03_PGRAPH_Y_MISC 0x00400504 +#define NV04_PGRAPH_VALID1 0x00400508 +#define NV04_PGRAPH_SOURCE_COLOR 0x0040050C +#define NV04_PGRAPH_MISC24_0 0x00400510 +#define NV03_PGRAPH_XY_LOGIC_MISC0 0x00400514 +#define NV03_PGRAPH_XY_LOGIC_MISC1 0x00400518 +#define NV03_PGRAPH_XY_LOGIC_MISC2 0x0040051C +#define NV03_PGRAPH_XY_LOGIC_MISC3 0x00400520 +#define NV03_PGRAPH_CLIPX_0 0x00400524 +#define NV03_PGRAPH_CLIPX_1 0x00400528 +#define NV03_PGRAPH_CLIPY_0 0x0040052C +#define NV03_PGRAPH_CLIPY_1 0x00400530 +#define NV03_PGRAPH_ABS_ICLIP_XMAX 0x00400534 +#define NV03_PGRAPH_ABS_ICLIP_YMAX 0x00400538 +#define NV03_PGRAPH_ABS_UCLIP_XMIN 0x0040053C +#define NV03_PGRAPH_ABS_UCLIP_YMIN 0x00400540 +#define NV03_PGRAPH_ABS_UCLIP_XMAX 0x00400544 +#define NV03_PGRAPH_ABS_UCLIP_YMAX 0x00400548 +#define NV03_PGRAPH_ABS_UCLIPA_XMIN 0x00400560 +#define NV03_PGRAPH_ABS_UCLIPA_YMIN 0x00400564 +#define NV03_PGRAPH_ABS_UCLIPA_XMAX 0x00400568 +#define NV03_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C +#define NV04_PGRAPH_MISC24_1 0x00400570 +#define NV04_PGRAPH_MISC24_2 0x00400574 +#define NV04_PGRAPH_VALID2 0x00400578 +#define NV04_PGRAPH_PASSTHRU_0 0x0040057C +#define NV04_PGRAPH_PASSTHRU_1 0x00400580 +#define NV04_PGRAPH_PASSTHRU_2 0x00400584 +#define NV10_PGRAPH_DIMX_TEXTURE 0x00400588 +#define NV10_PGRAPH_WDIMX_TEXTURE 0x0040058C +#define NV04_PGRAPH_COMBINE_0_ALPHA 0x00400590 +#define NV04_PGRAPH_COMBINE_0_COLOR 0x00400594 +#define NV04_PGRAPH_COMBINE_1_ALPHA 0x00400598 +#define NV04_PGRAPH_COMBINE_1_COLOR 0x0040059C +#define NV04_PGRAPH_FORMAT_0 0x004005A8 +#define NV04_PGRAPH_FORMAT_1 0x004005AC +#define NV04_PGRAPH_FILTER_0 0x004005B0 +#define NV04_PGRAPH_FILTER_1 0x004005B4 +#define NV03_PGRAPH_MONO_COLOR0 0x00400600 +#define NV04_PGRAPH_ROP3 0x00400604 +#define NV04_PGRAPH_BETA_AND 0x00400608 +#define NV04_PGRAPH_BETA_PREMULT 0x0040060C +#define NV04_PGRAPH_FORMATS 0x00400618 +#define NV04_PGRAPH_BOFFSET0 0x00400640 +#define NV04_PGRAPH_BOFFSET1 0x00400644 +#define NV04_PGRAPH_BOFFSET2 0x00400648 +#define NV04_PGRAPH_BOFFSET3 0x0040064C +#define NV04_PGRAPH_BOFFSET4 0x00400650 +#define NV04_PGRAPH_BOFFSET5 0x00400654 +#define NV04_PGRAPH_BBASE0 0x00400658 +#define NV04_PGRAPH_BBASE1 0x0040065C +#define NV04_PGRAPH_BBASE2 0x00400660 +#define NV04_PGRAPH_BBASE3 0x00400664 +#define NV04_PGRAPH_BBASE4 0x00400668 +#define NV04_PGRAPH_BBASE5 0x0040066C +#define NV04_PGRAPH_BPITCH0 0x00400670 +#define NV04_PGRAPH_BPITCH1 0x00400674 +#define NV04_PGRAPH_BPITCH2 0x00400678 +#define NV04_PGRAPH_BPITCH3 0x0040067C +#define NV04_PGRAPH_BPITCH4 0x00400680 +#define NV04_PGRAPH_BLIMIT0 0x00400684 +#define NV04_PGRAPH_BLIMIT1 0x00400688 +#define NV04_PGRAPH_BLIMIT2 0x0040068C +#define NV04_PGRAPH_BLIMIT3 0x00400690 +#define NV04_PGRAPH_BLIMIT4 0x00400694 +#define NV04_PGRAPH_BLIMIT5 0x00400698 +#define NV04_PGRAPH_BSWIZZLE2 0x0040069C +#define NV04_PGRAPH_BSWIZZLE5 0x004006A0 +#define NV04_PGRAPH_SURFACE 0x0040070C +#define NV04_PGRAPH_STATE 0x00400710 +#define NV10_PGRAPH_SURFACE 0x00400710 +#define NV04_PGRAPH_NOTIFY 0x00400714 +#define NV10_PGRAPH_STATE 0x00400714 +#define NV10_PGRAPH_NOTIFY 0x00400718 -#define NV_PGRAPH_FIFO 0x00400720 +#define NV04_PGRAPH_FIFO 0x00400720 + +#define NV04_PGRAPH_BPIXEL 0x00400724 +#define NV10_PGRAPH_RDI_INDEX 0x00400750 +#define NV04_PGRAPH_FFINTFC_ST2 0x00400754 +#define NV10_PGRAPH_RDI_DATA 0x00400754 +#define NV04_PGRAPH_DMA_PITCH 0x00400760 +#define NV10_PGRAPH_FFINTFC_ST2 0x00400764 +#define NV04_PGRAPH_DVD_COLORFMT 0x00400764 +#define NV04_PGRAPH_SCALED_FORMAT 0x00400768 +#define NV10_PGRAPH_DMA_PITCH 0x00400770 +#define NV10_PGRAPH_DVD_COLORFMT 0x00400774 +#define NV10_PGRAPH_SCALED_FORMAT 0x00400778 +#define NV10_PGRAPH_CHANNEL_CTX_TABLE 0x00400780 +#define NV10_PGRAPH_CHANNEL_CTX_SIZE 0x00400784 +#define NV10_PGRAPH_CHANNEL_CTX_POINTER 0x00400788 +#define NV04_PGRAPH_PATT_COLOR0 0x00400800 +#define NV04_PGRAPH_PATT_COLOR1 0x00400804 +#define NV04_PGRAPH_PATTERN 0x00400808 +#define NV04_PGRAPH_PATTERN_SHAPE 0x00400810 +#define NV04_PGRAPH_CHROMA 0x00400814 +#define NV04_PGRAPH_CONTROL0 0x00400818 +#define NV04_PGRAPH_CONTROL1 0x0040081C +#define NV04_PGRAPH_CONTROL2 0x00400820 +#define NV04_PGRAPH_BLEND 0x00400824 +#define NV04_PGRAPH_STORED_FMT 0x00400830 +#define NV04_PGRAPH_PATT_COLORRAM 0x00400900 +#define NV04_PGRAPH_U_RAM 0x00400D00 +#define NV04_PGRAPH_V_RAM 0x00400D40 +#define NV04_PGRAPH_W_RAM 0x00400D80 +#define NV10_PGRAPH_WINDOWCLIP_HORIZONTAL 0x00400F00 +#define NV10_PGRAPH_WINDOWCLIP_VERTICAL 0x00400F20 +#define NV10_PGRAPH_XFMODE0 0x00400F40 +#define NV10_PGRAPH_XFMODE1 0x00400F44 +#define NV10_PGRAPH_GLOBALSTATE0 0x00400F48 +#define NV10_PGRAPH_GLOBALSTATE1 0x00400F4C +#define NV10_PGRAPH_PIPE_ADDRESS 0x00400F50 +#define NV10_PGRAPH_PIPE_DATA 0x00400F54 +#define NV04_PGRAPH_DMA_START_0 0x00401000 +#define NV04_PGRAPH_DMA_START_1 0x00401004 +#define NV04_PGRAPH_DMA_LENGTH 0x00401008 +#define NV04_PGRAPH_DMA_MISC 0x0040100C +#define NV04_PGRAPH_DMA_DATA_0 0x00401020 +#define NV04_PGRAPH_DMA_DATA_1 0x00401024 +#define NV04_PGRAPH_DMA_RM 0x00401030 +#define NV04_PGRAPH_DMA_A_XLATE_INST 0x00401040 +#define NV04_PGRAPH_DMA_A_CONTROL 0x00401044 +#define NV04_PGRAPH_DMA_A_LIMIT 0x00401048 +#define NV04_PGRAPH_DMA_A_TLB_PTE 0x0040104C +#define NV04_PGRAPH_DMA_A_TLB_TAG 0x00401050 +#define NV04_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054 +#define NV04_PGRAPH_DMA_A_OFFSET 0x00401058 +#define NV04_PGRAPH_DMA_A_SIZE 0x0040105C +#define NV04_PGRAPH_DMA_A_Y_SIZE 0x00401060 +#define NV04_PGRAPH_DMA_B_XLATE_INST 0x00401080 +#define NV04_PGRAPH_DMA_B_CONTROL 0x00401084 +#define NV04_PGRAPH_DMA_B_LIMIT 0x00401088 +#define NV04_PGRAPH_DMA_B_TLB_PTE 0x0040108C +#define NV04_PGRAPH_DMA_B_TLB_TAG 0x00401090 +#define NV04_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094 +#define NV04_PGRAPH_DMA_B_OFFSET 0x00401098 +#define NV04_PGRAPH_DMA_B_SIZE 0x0040109C +#define NV04_PGRAPH_DMA_B_Y_SIZE 0x004010A0 -#define NV_PGRAPH_BPIXEL 0x00400724 -#define NV_PGRAPH_RDI_INDEX 0x00400750 -#define NV_PGRAPH_RDI_DATA 0x00400754 -#define NV_PGRAPH_FFINTFC_ST2 0x00400764 -#define NV_PGRAPH_DMA_PITCH 0x00400770 -#define NV_PGRAPH_DVD_COLORFMT 0x00400774 -#define NV_PGRAPH_SCALED_FORMAT 0x00400778 -#define NV_PGRAPH_CHANNEL_CTX_TABLE 0x00400780 -#define NV_PGRAPH_CHANNEL_CTX_SIZE 0x00400784 -#define NV_PGRAPH_CHANNEL_CTX_POINTER 0x00400788 -#define NV_PGRAPH_PATT_COLOR0 0x00400800 -#define NV_PGRAPH_PATT_COLOR1 0x00400804 -#define NV_PGRAPH_PATTERN_SHAPE 0x00400810 -#define NV_PGRAPH_CHROMA 0x00400814 -#define NV_PGRAPH_STORED_FMT 0x00400830 -#define NV_PGRAPH_XFMODE0 0x00400F40 -#define NV_PGRAPH_XFMODE1 0x00400F44 -#define NV_PGRAPH_GLOBALSTATE0 0x00400F48 -#define NV_PGRAPH_GLOBALSTATE1 0x00400F4C -#define NV_PGRAPH_PIPE_ADDRESS 0x00400F50 -#define NV_PGRAPH_PIPE_DATA 0x00400F54 -#define NV_PGRAPH_DMA_START_0 0x00401000 -#define NV_PGRAPH_DMA_START_1 0x00401004 -#define NV_PGRAPH_DMA_LENGTH 0x00401008 -#define NV_PGRAPH_DMA_MISC 0x0040100C /* It's a guess that this works on NV03. Confirmed on NV04, though */ -#define NV_PFIFO_DELAY_0 0x00002040 -#define NV_PFIFO_DMA_TIMESLICE 0x00002044 -#define NV_PFIFO_INTSTAT 0x00002100 -#define NV_PFIFO_INTEN 0x00002140 +#define NV04_PFIFO_DELAY_0 0x00002040 +#define NV04_PFIFO_DMA_TIMESLICE 0x00002044 +#define NV04_PFIFO_NEXT_CHANNEL 0x00002050 +#define NV03_PFIFO_INTR_0 0x00002100 +#define NV03_PFIFO_INTR_EN_0 0x00002140 # define NV_PFIFO_INTR_CACHE_ERROR (1<< 0) # define NV_PFIFO_INTR_RUNOUT (1<< 4) # define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1<< 8) @@ -177,105 +246,108 @@ # define NV_PFIFO_INTR_DMA_PT (1<<16) # define NV_PFIFO_INTR_SEMAPHORE (1<<20) # define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1<<24) -#define NV_PFIFO_RAMHT 0x00002210 -#define NV_PFIFO_RAMFC 0x00002214 -#define NV_PFIFO_RAMRO 0x00002218 +#define NV03_PFIFO_RAMHT 0x00002210 +#define NV03_PFIFO_RAMFC 0x00002214 +#define NV03_PFIFO_RAMRO 0x00002218 #define NV40_PFIFO_RAMFC 0x00002220 -#define NV_PFIFO_CACHES 0x00002500 -#define NV_PFIFO_MODE 0x00002504 -#define NV_PFIFO_DMA 0x00002508 -#define NV_PFIFO_SIZE 0x0000250c -#define NV_PFIFO_CACH0_PSH0 0x00003000 -#define NV_PFIFO_CACH0_PUL0 0x00003050 -#define NV_PFIFO_CACH0_PUL1 0x00003054 -#define NV_PFIFO_CACH1_PSH0 0x00003200 -#define NV_PFIFO_CACH1_PSH1 0x00003204 -#define NV_PFIFO_CACH1_DMAPSH 0x00003220 -#define NV_PFIFO_CACH1_DMAF 0x00003224 -# define NV_PFIFO_CACH1_DMAF_TRIG_8_BYTES 0x00000000 -# define NV_PFIFO_CACH1_DMAF_TRIG_16_BYTES 0x00000008 -# define NV_PFIFO_CACH1_DMAF_TRIG_24_BYTES 0x00000010 -# define NV_PFIFO_CACH1_DMAF_TRIG_32_BYTES 0x00000018 -# define NV_PFIFO_CACH1_DMAF_TRIG_40_BYTES 0x00000020 -# define NV_PFIFO_CACH1_DMAF_TRIG_48_BYTES 0x00000028 -# define NV_PFIFO_CACH1_DMAF_TRIG_56_BYTES 0x00000030 -# define NV_PFIFO_CACH1_DMAF_TRIG_64_BYTES 0x00000038 -# define NV_PFIFO_CACH1_DMAF_TRIG_72_BYTES 0x00000040 -# define NV_PFIFO_CACH1_DMAF_TRIG_80_BYTES 0x00000048 -# define NV_PFIFO_CACH1_DMAF_TRIG_88_BYTES 0x00000050 -# define NV_PFIFO_CACH1_DMAF_TRIG_96_BYTES 0x00000058 -# define NV_PFIFO_CACH1_DMAF_TRIG_104_BYTES 0x00000060 -# define NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES 0x00000068 -# define NV_PFIFO_CACH1_DMAF_TRIG_120_BYTES 0x00000070 -# define NV_PFIFO_CACH1_DMAF_TRIG_128_BYTES 0x00000078 -# define NV_PFIFO_CACH1_DMAF_TRIG_136_BYTES 0x00000080 -# define NV_PFIFO_CACH1_DMAF_TRIG_144_BYTES 0x00000088 -# define NV_PFIFO_CACH1_DMAF_TRIG_152_BYTES 0x00000090 -# define NV_PFIFO_CACH1_DMAF_TRIG_160_BYTES 0x00000098 -# define NV_PFIFO_CACH1_DMAF_TRIG_168_BYTES 0x000000A0 -# define NV_PFIFO_CACH1_DMAF_TRIG_176_BYTES 0x000000A8 -# define NV_PFIFO_CACH1_DMAF_TRIG_184_BYTES 0x000000B0 -# define NV_PFIFO_CACH1_DMAF_TRIG_192_BYTES 0x000000B8 -# define NV_PFIFO_CACH1_DMAF_TRIG_200_BYTES 0x000000C0 -# define NV_PFIFO_CACH1_DMAF_TRIG_208_BYTES 0x000000C8 -# define NV_PFIFO_CACH1_DMAF_TRIG_216_BYTES 0x000000D0 -# define NV_PFIFO_CACH1_DMAF_TRIG_224_BYTES 0x000000D8 -# define NV_PFIFO_CACH1_DMAF_TRIG_232_BYTES 0x000000E0 -# define NV_PFIFO_CACH1_DMAF_TRIG_240_BYTES 0x000000E8 -# define NV_PFIFO_CACH1_DMAF_TRIG_248_BYTES 0x000000F0 -# define NV_PFIFO_CACH1_DMAF_TRIG_256_BYTES 0x000000F8 -# define NV_PFIFO_CACH1_DMAF_SIZE 0x0000E000 -# define NV_PFIFO_CACH1_DMAF_SIZE_32_BYTES 0x00000000 -# define NV_PFIFO_CACH1_DMAF_SIZE_64_BYTES 0x00002000 -# define NV_PFIFO_CACH1_DMAF_SIZE_96_BYTES 0x00004000 -# define NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES 0x00006000 -# define NV_PFIFO_CACH1_DMAF_SIZE_160_BYTES 0x00008000 -# define NV_PFIFO_CACH1_DMAF_SIZE_192_BYTES 0x0000A000 -# define NV_PFIFO_CACH1_DMAF_SIZE_224_BYTES 0x0000C000 -# define NV_PFIFO_CACH1_DMAF_SIZE_256_BYTES 0x0000E000 -# define NV_PFIFO_CACH1_DMAF_MAX_REQS 0x001F0000 -# define NV_PFIFO_CACH1_DMAF_MAX_REQS_0 0x00000000 -# define NV_PFIFO_CACH1_DMAF_MAX_REQS_1 0x00010000 -# define NV_PFIFO_CACH1_DMAF_MAX_REQS_2 0x00020000 -# define NV_PFIFO_CACH1_DMAF_MAX_REQS_3 0x00030000 -# define NV_PFIFO_CACH1_DMAF_MAX_REQS_4 0x00040000 -# define NV_PFIFO_CACH1_DMAF_MAX_REQS_5 0x00050000 -# define NV_PFIFO_CACH1_DMAF_MAX_REQS_6 0x00060000 -# define NV_PFIFO_CACH1_DMAF_MAX_REQS_7 0x00070000 -# define NV_PFIFO_CACH1_DMAF_MAX_REQS_8 0x00080000 -# define NV_PFIFO_CACH1_DMAF_MAX_REQS_9 0x00090000 -# define NV_PFIFO_CACH1_DMAF_MAX_REQS_10 0x000A0000 -# define NV_PFIFO_CACH1_DMAF_MAX_REQS_11 0x000B0000 -# define NV_PFIFO_CACH1_DMAF_MAX_REQS_12 0x000C0000 -# define NV_PFIFO_CACH1_DMAF_MAX_REQS_13 0x000D0000 -# define NV_PFIFO_CACH1_DMAF_MAX_REQS_14 0x000E0000 -# define NV_PFIFO_CACH1_DMAF_MAX_REQS_15 0x000F0000 -# define NV_PFIFO_CACH1_ENDIAN 0x80000000 -# define NV_PFIFO_CACH1_LITTLE_ENDIAN 0x7FFFFFFF -# define NV_PFIFO_CACH1_BIG_ENDIAN 0x80000000 -#define NV_PFIFO_CACH1_DMAS 0x00003228 -#define NV_PFIFO_CACH1_DMAI 0x0000322c -#define NV_PFIFO_CACH1_DMAC 0x00003230 -#define NV_PFIFO_CACH1_DMAP 0x00003240 -#define NV_PFIFO_CACH1_DMAG 0x00003244 -#define NV_PFIFO_CACH1_REF_CNT 0x00003248 -#define NV_PFIFO_CACH1_DMASR 0x0000324C -#define NV_PFIFO_CACH1_PUL0 0x00003250 -#define NV_PFIFO_CACH1_PUL1 0x00003254 -#define NV_PFIFO_CACH1_HASH 0x00003258 -#define NV_PFIFO_CACH1_ACQUIRE_TIMEOUT 0x00003260 -#define NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP 0x00003264 -#define NV_PFIFO_CACH1_ACQUIRE_VALUE 0x00003268 -#define NV_PFIFO_CACH1_SEMAPHORE 0x0000326C -#define NV_PFIFO_CACH1_GET 0x00003270 -#define NV_PFIFO_CACH1_ENG 0x00003280 -#define NV_PFIFO_CACH1_DMA_DCOUNT 0x000032A0 +#define NV03_PFIFO_CACHES 0x00002500 +#define NV04_PFIFO_MODE 0x00002504 +#define NV04_PFIFO_DMA 0x00002508 +#define NV04_PFIFO_SIZE 0x0000250c +#define NV03_PFIFO_CACHE0_PUSH0 0x00003000 +#define NV03_PFIFO_CACHE0_PULL0 0x00003040 +#define NV04_PFIFO_CACHE0_PULL0 0x00003050 +#define NV04_PFIFO_CACHE0_PULL1 0x00003054 +#define NV03_PFIFO_CACHE1_PUSH0 0x00003200 +#define NV03_PFIFO_CACHE1_PUSH1 0x00003204 +#define NV04_PFIFO_CACHE1_DMA_PUSH 0x00003220 +#define NV04_PFIFO_CACHE1_DMA_FETCH 0x00003224 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000008 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000010 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000018 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000020 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000028 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000030 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000038 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000040 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000048 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x00000050 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x00000058 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x00000060 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x00000068 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x00000070 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x00000078 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000080 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000088 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000090 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000098 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x000000A0 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x000000A8 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x000000B0 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x000000B8 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x000000C0 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x000000C8 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x000000D0 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x000000D8 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x000000E0 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x000000E8 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x000000F0 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x000000F8 +# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 0x0000E000 +# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000 +# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00002000 +# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00004000 +# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00006000 +# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00008000 +# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x0000A000 +# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x0000C000 +# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x0000E000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 0x001F0000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00010000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00020000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00030000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00040000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00050000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00060000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00070000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00080000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00090000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x000A0000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x000B0000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x000C0000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x000D0000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x000E0000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x000F0000 +# define NV_PFIFO_CACHE1_ENDIAN 0x80000000 +# define NV_PFIFO_CACHE1_LITTLE_ENDIAN 0x7FFFFFFF +# define NV_PFIFO_CACHE1_BIG_ENDIAN 0x80000000 +#define NV04_PFIFO_CACHE1_DMA_STATE 0x00003228 +#define NV04_PFIFO_CACHE1_DMA_INSTANCE 0x0000322c +#define NV04_PFIFO_CACHE1_DMA_CTL 0x00003230 +#define NV04_PFIFO_CACHE1_DMA_PUT 0x00003240 +#define NV04_PFIFO_CACHE1_DMA_GET 0x00003244 +#define NV10_PFIFO_CACHE1_REF_CNT 0x00003248 +#define NV10_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C +#define NV03_PFIFO_CACHE1_PULL0 0x00003240 +#define NV04_PFIFO_CACHE1_PULL0 0x00003250 +#define NV03_PFIFO_CACHE1_PULL1 0x00003250 +#define NV04_PFIFO_CACHE1_PULL1 0x00003254 +#define NV04_PFIFO_CACHE1_HASH 0x00003258 +#define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT 0x00003260 +#define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP 0x00003264 +#define NV10_PFIFO_CACHE1_ACQUIRE_VALUE 0x00003268 +#define NV10_PFIFO_CACHE1_SEMAPHORE 0x0000326C +#define NV03_PFIFO_CACHE1_GET 0x00003270 +#define NV04_PFIFO_CACHE1_ENGINE 0x00003280 +#define NV10_PFIFO_CACHE1_DMA_DCOUNT 0x000032A0 #define NV40_PFIFO_GRCTX_INSTANCE 0x000032E0 #define NV40_PFIFO_UNK32E4 0x000032E4 -#define NV_PFIFO_CACH1_METHOD(i) (0x00003800+(i*8)) -#define NV_PFIFO_CACH1_DATA(i) (0x00003804+(i*8)) -#define NV40_PFIFO_CACH1_METHOD(i) (0x00090000+(i*8)) -#define NV40_PFIFO_CACH1_DATA(i) (0x00090004+(i*8)) +#define NV04_PFIFO_CACHE1_METHOD(i) (0x00003800+(i*8)) +#define NV04_PFIFO_CACHE1_DATA(i) (0x00003804+(i*8)) +#define NV40_PFIFO_CACHE1_METHOD(i) (0x00090000+(i*8)) +#define NV40_PFIFO_CACHE1_DATA(i) (0x00090004+(i*8)) #define NV_CRTC0_INTSTAT 0x00600100 #define NV_CRTC0_INTEN 0x00600140 diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index fb35ba74..f1f272e7 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -83,6 +83,12 @@ int nouveau_firstopen(struct drm_device *dev) } else dev_priv->ramin = NULL; + /* Determine exact chipset we're running on */ + if (dev_priv->card_type < NV_10) + dev_priv->chipset = dev_priv->card_type; + else + dev_priv->chipset =(NV_READ(NV03_PMC_BOOT_0) & 0x0ff00000) >> 20; + /* Clear RAMIN * Determine locations for RAMHT/FC/RO * Initialise PFIFO @@ -102,6 +108,8 @@ int nouveau_firstopen(struct drm_device *dev) nv20_graph_init(dev); else if (dev_priv->card_type >= NV_10) nv10_graph_init(dev); + else if (dev_priv->card_type >= NV_04) + nv04_graph_init(dev); return 0; } diff --git a/shared-core/nv04_graph.c b/shared-core/nv04_graph.c new file mode 100644 index 00000000..830d673e --- /dev/null +++ b/shared-core/nv04_graph.c @@ -0,0 +1,234 @@ +/* + * Copyright 2007 Stephane Marchesin + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "drmP.h" +#include "drm.h" +#include "nouveau_drm.h" +#include "nouveau_drv.h" + +struct reg_interval +{ + uint32_t reg; + int number; +} nv04_graph_ctx_regs [] = { + {NV04_PGRAPH_CTX_SWITCH1, 1}, + {NV04_PGRAPH_CTX_SWITCH2, 1}, + {NV04_PGRAPH_CTX_SWITCH3, 1}, + {NV04_PGRAPH_CTX_SWITCH4, 1}, + {NV04_PGRAPH_CTX_USER, 1}, + {NV04_PGRAPH_CTX_CACHE1, 8}, + {NV04_PGRAPH_CTX_CACHE2, 8}, + {NV04_PGRAPH_CTX_CACHE3, 8}, + {NV04_PGRAPH_CTX_CACHE4, 8}, + {NV03_PGRAPH_ABS_X_RAM, 32}, + {NV03_PGRAPH_ABS_Y_RAM, 32}, + {NV03_PGRAPH_X_MISC, 1}, + {NV03_PGRAPH_Y_MISC, 1}, + {NV04_PGRAPH_VALID1, 1}, + {NV04_PGRAPH_SOURCE_COLOR, 1}, + {NV04_PGRAPH_MISC24_0, 1}, + {NV03_PGRAPH_XY_LOGIC_MISC0, 1}, + {NV03_PGRAPH_XY_LOGIC_MISC1, 1}, + {NV03_PGRAPH_XY_LOGIC_MISC2, 1}, + {NV03_PGRAPH_XY_LOGIC_MISC3, 1}, + {NV03_PGRAPH_CLIPX_0, 1}, + {NV03_PGRAPH_CLIPX_1, 1}, + {NV03_PGRAPH_CLIPY_0, 1}, + {NV03_PGRAPH_CLIPY_1, 1}, + {NV03_PGRAPH_ABS_ICLIP_XMAX, 1}, + {NV03_PGRAPH_ABS_ICLIP_YMAX, 1}, + {NV03_PGRAPH_ABS_UCLIP_XMIN, 1}, + {NV03_PGRAPH_ABS_UCLIP_YMIN, 1}, + {NV03_PGRAPH_ABS_UCLIP_XMAX, 1}, + {NV03_PGRAPH_ABS_UCLIP_YMAX, 1}, + {NV03_PGRAPH_ABS_UCLIPA_XMIN, 1}, + {NV03_PGRAPH_ABS_UCLIPA_YMIN, 1}, + {NV03_PGRAPH_ABS_UCLIPA_XMAX, 1}, + {NV03_PGRAPH_ABS_UCLIPA_YMAX, 1}, + {NV04_PGRAPH_MISC24_1, 1}, + {NV04_PGRAPH_MISC24_2, 1}, + {NV04_PGRAPH_VALID2, 1}, + {NV04_PGRAPH_PASSTHRU_0, 1}, + {NV04_PGRAPH_PASSTHRU_1, 1}, + {NV04_PGRAPH_PASSTHRU_2, 1}, + {NV04_PGRAPH_COMBINE_0_ALPHA, 1}, + {NV04_PGRAPH_COMBINE_0_COLOR, 1}, + {NV04_PGRAPH_COMBINE_1_ALPHA, 1}, + {NV04_PGRAPH_COMBINE_1_COLOR, 1}, + // texture state + {NV04_PGRAPH_FORMAT_0, 1}, + {NV04_PGRAPH_FORMAT_1, 1}, + {NV04_PGRAPH_FILTER_0, 1}, + {NV04_PGRAPH_FILTER_1, 1}, + // vertex state + {0x004005c0, 1}, + {0x004005c4, 1}, + {0x004005c8, 1}, + {0x004005cc, 1}, + {0x004005d0, 1}, + {0x004005d4, 1}, + {0x004005d8, 1}, + {0x004005dc, 1}, + {0x004005e0, 1}, + {NV03_PGRAPH_MONO_COLOR0, 1}, + {NV04_PGRAPH_ROP3, 1}, + {NV04_PGRAPH_BETA_AND, 1}, + {NV04_PGRAPH_BETA_PREMULT, 1}, + {NV04_PGRAPH_FORMATS, 1}, + {NV04_PGRAPH_BOFFSET0, 6}, + {NV04_PGRAPH_BBASE0, 6}, + {NV04_PGRAPH_BPITCH0, 5}, + {NV04_PGRAPH_BLIMIT0, 6}, + {NV04_PGRAPH_BSWIZZLE2, 1}, + {NV04_PGRAPH_BSWIZZLE5, 1}, + {NV04_PGRAPH_SURFACE, 1}, + {NV04_PGRAPH_STATE, 1}, + {NV04_PGRAPH_NOTIFY, 1}, + {NV04_PGRAPH_BPIXEL, 1}, + {NV04_PGRAPH_DMA_PITCH, 1}, + {NV04_PGRAPH_DVD_COLORFMT, 1}, + {NV04_PGRAPH_SCALED_FORMAT, 1}, + {NV04_PGRAPH_PATT_COLOR0, 1}, + {NV04_PGRAPH_PATT_COLOR1, 1}, + {NV04_PGRAPH_PATTERN, 2}, + {NV04_PGRAPH_PATTERN_SHAPE, 1}, + {NV04_PGRAPH_CHROMA, 1}, + {NV04_PGRAPH_CONTROL0, 1}, + {NV04_PGRAPH_CONTROL1, 1}, + {NV04_PGRAPH_CONTROL2, 1}, + {NV04_PGRAPH_BLEND, 1}, + {NV04_PGRAPH_STORED_FMT, 1}, + {NV04_PGRAPH_PATT_COLORRAM, 64}, + {NV04_PGRAPH_U_RAM, 16}, + {NV04_PGRAPH_V_RAM, 16}, + {NV04_PGRAPH_W_RAM, 16}, + {NV04_PGRAPH_DMA_START_0, 1}, + {NV04_PGRAPH_DMA_START_1, 1}, + {NV04_PGRAPH_DMA_LENGTH, 1}, + {NV04_PGRAPH_DMA_MISC, 1}, + {NV04_PGRAPH_DMA_DATA_0, 1}, + {NV04_PGRAPH_DMA_DATA_1, 1}, + {NV04_PGRAPH_DMA_RM, 1}, + {NV04_PGRAPH_DMA_A_XLATE_INST, 1}, + {NV04_PGRAPH_DMA_A_CONTROL, 1}, + {NV04_PGRAPH_DMA_A_LIMIT, 1}, + {NV04_PGRAPH_DMA_A_TLB_PTE, 1}, + {NV04_PGRAPH_DMA_A_TLB_TAG, 1}, + {NV04_PGRAPH_DMA_A_ADJ_OFFSET, 1}, + {NV04_PGRAPH_DMA_A_OFFSET, 1}, + {NV04_PGRAPH_DMA_A_SIZE, 1}, + {NV04_PGRAPH_DMA_A_Y_SIZE, 1}, + {NV04_PGRAPH_DMA_B_XLATE_INST, 1}, + {NV04_PGRAPH_DMA_B_CONTROL, 1}, + {NV04_PGRAPH_DMA_B_LIMIT, 1}, + {NV04_PGRAPH_DMA_B_TLB_PTE, 1}, + {NV04_PGRAPH_DMA_B_TLB_TAG, 1}, + {NV04_PGRAPH_DMA_B_ADJ_OFFSET, 1}, + {NV04_PGRAPH_DMA_B_OFFSET, 1}, + {NV04_PGRAPH_DMA_B_SIZE, 1}, + {NV04_PGRAPH_DMA_B_Y_SIZE, 1}, +}; + +void nouveau_nv04_context_switch(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + int channel, channel_old, i, j, index; + + channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); + channel_old = (NV_READ(NV04_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); + + DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel); + + NV_WRITE(NV03_PFIFO_CACHES, 0x0); + NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0); + NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x0); + NV_WRITE(NV04_PGRAPH_FIFO,0x0); + + // save PGRAPH context + index=0; + for (i = 0; i<sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++) + for (j = 0; j<nv04_graph_ctx_regs[i].number; j++) + { + dev_priv->fifos[channel_old].pgraph_ctx[index] = NV_READ(nv04_graph_ctx_regs[i].reg+j*4); + index++; + } + + nouveau_wait_for_idle(dev); + + NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10000000); + NV_WRITE(NV04_PGRAPH_CTX_USER, (NV_READ(NV04_PGRAPH_CTX_USER) & 0xffffff) | (0x0f << 24)); + + nouveau_wait_for_idle(dev); + // restore PGRAPH context + //XXX not working yet +#if 1 + index=0; + for (i = 0; i<sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++) + for (j = 0; j<nv04_graph_ctx_regs[i].number; j++) + { + NV_WRITE(nv04_graph_ctx_regs[i].reg+j*4, dev_priv->fifos[channel].pgraph_ctx[index]); + index++; + } + nouveau_wait_for_idle(dev); +#endif + + NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10010100); + NV_WRITE(NV04_PGRAPH_CTX_USER, channel << 24); + NV_WRITE(NV04_PGRAPH_FFINTFC_ST2, NV_READ(NV04_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); + + NV_WRITE(NV04_PGRAPH_FIFO,0x0); + NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0); + NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x1); + NV_WRITE(NV03_PFIFO_CACHES, 0x1); + NV_WRITE(NV04_PGRAPH_FIFO,0x1); +} + +int nv04_graph_context_create(drm_device_t *dev, int channel) { + drm_nouveau_private_t *dev_priv = dev->dev_private; + DRM_DEBUG("nv04_graph_context_create %d\n", channel); + + memset(dev_priv->fifos[channel].pgraph_ctx, 0, sizeof(dev_priv->fifos[channel].pgraph_ctx)); + + //dev_priv->fifos[channel].pgraph_ctx_user = channel << 24; + dev_priv->fifos[channel].pgraph_ctx[0] = 0x0001ffff; + /* is it really needed ??? */ + //dev_priv->fifos[channel].pgraph_ctx[1] = NV_READ(NV_PGRAPH_DEBUG_4); + //dev_priv->fifos[channel].pgraph_ctx[2] = NV_READ(0x004006b0); + + return 0; +} + + +int nv04_graph_init(drm_device_t *dev) { + drm_nouveau_private_t *dev_priv = dev->dev_private; + + // check the context is big enough + int i,sum=0; + for ( i = 0 ; i<sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++) + sum+=nv04_graph_ctx_regs[i].number; + if ( sum*4>sizeof(dev_priv->fifos[0].pgraph_ctx) ) + DRM_ERROR("pgraph_ctx too small\n"); + return 0; +} + diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index ccbb34de..ad74b840 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -34,149 +34,149 @@ static void nv10_praph_pipe(drm_device_t *dev) { nouveau_wait_for_idle(dev); /* XXX check haiku comments */ - NV_WRITE(NV_PGRAPH_XFMODE0, 0x10000000); - NV_WRITE(NV_PGRAPH_XFMODE1, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x000064c0); + NV_WRITE(NV10_PGRAPH_XFMODE0, 0x10000000); + NV_WRITE(NV10_PGRAPH_XFMODE1, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); for (i = 0; i < 4; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); for (i = 0; i < 4; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006ab0); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); for (i = 0; i < 3; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006a80); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); for (i = 0; i < 3; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000040); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000008); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000008); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000200); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000200); for (i = 0; i < 48; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); nouveau_wait_for_idle(dev); - NV_WRITE(NV_PGRAPH_XFMODE0, 0x00000000); - NV_WRITE(NV_PGRAPH_XFMODE1, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006400); + NV_WRITE(NV10_PGRAPH_XFMODE0, 0x00000000); + NV_WRITE(NV10_PGRAPH_XFMODE1, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006400); for (i = 0; i < 211; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); - - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006800); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); + + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006800); for (i = 0; i < 162; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); for (i = 0; i < 25; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006c00); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0xbf800000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00007000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006c00); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0xbf800000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00007000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); for (i = 0; i < 35; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00007400); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00007400); for (i = 0; i < 48; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00007800); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00007800); for (i = 0; i < 48; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00004400); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00004400); for (i = 0; i < 32; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000000); for (i = 0; i < 16; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000040); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); for (i = 0; i < 4; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); nouveau_wait_for_idle(dev); } @@ -184,20 +184,18 @@ static void nv10_praph_pipe(drm_device_t *dev) { /* TODO replace address with name use loops */ static int nv10_graph_ctx_regs [] = { -NV_PGRAPH_XY_LOGIC_MISC0, -NV_PGRAPH_DEBUG_4, -0x004006b0, - -NV_PGRAPH_CTX_SWITCH1, -NV_PGRAPH_CTX_SWITCH2, -NV_PGRAPH_CTX_SWITCH3, -NV_PGRAPH_CTX_SWITCH4, -NV_PGRAPH_CTX_SWITCH5, -0x00400160, -0x00400180, -0x004001a0, -0x004001c0, -0x004001e0, +NV03_PGRAPH_XY_LOGIC_MISC0, + +//NV10_PGRAPH_CTX_SWITCH1, make ctx switch crash +NV10_PGRAPH_CTX_SWITCH2, +NV10_PGRAPH_CTX_SWITCH3, +NV10_PGRAPH_CTX_SWITCH4, +NV10_PGRAPH_CTX_SWITCH5, +NV10_PGRAPH_CTX_CACHE1, /* 8 values from 0x400160 to 0x40017c */ +NV10_PGRAPH_CTX_CACHE2, /* 8 values from 0x400180 to 0x40019c */ +NV10_PGRAPH_CTX_CACHE3, /* 8 values from 0x4001a0 to 0x4001bc */ +NV10_PGRAPH_CTX_CACHE4, /* 8 values from 0x4001c0 to 0x4001dc */ +NV10_PGRAPH_CTX_CACHE5, /* 8 values from 0x4001e0 to 0x4001fc */ 0x00400164, 0x00400184, 0x004001a4, @@ -233,44 +231,44 @@ NV_PGRAPH_CTX_SWITCH5, 0x004001bc, 0x004001dc, 0x004001fc, -NV_PGRAPH_CTX_USER, -NV_PGRAPH_DMA_START_0, -NV_PGRAPH_DMA_START_1, -NV_PGRAPH_DMA_LENGTH, -NV_PGRAPH_DMA_MISC, -NV_PGRAPH_DMA_PITCH, -NV_PGRAPH_BOFFSET0, -NV_PGRAPH_BBASE0, -NV_PGRAPH_BLIMIT0, -NV_PGRAPH_BOFFSET1, -NV_PGRAPH_BBASE1, -NV_PGRAPH_BLIMIT1, -NV_PGRAPH_BOFFSET2, -NV_PGRAPH_BBASE2, -NV_PGRAPH_BLIMIT2, -NV_PGRAPH_BOFFSET3, -NV_PGRAPH_BBASE3, -NV_PGRAPH_BLIMIT3, -NV_PGRAPH_BOFFSET4, -NV_PGRAPH_BBASE4, -NV_PGRAPH_BLIMIT4, -NV_PGRAPH_BOFFSET5, -NV_PGRAPH_BBASE5, -NV_PGRAPH_BLIMIT5, -NV_PGRAPH_BPITCH0, -NV_PGRAPH_BPITCH1, -NV_PGRAPH_BPITCH2, -NV_PGRAPH_BPITCH3, -NV_PGRAPH_BPITCH4, -NV_PGRAPH_SURFACE, -NV_PGRAPH_STATE, -NV_PGRAPH_BSWIZZLE2, -NV_PGRAPH_BSWIZZLE5, -NV_PGRAPH_BPIXEL, -NV_PGRAPH_NOTIFY, -NV_PGRAPH_PATT_COLOR0, -NV_PGRAPH_PATT_COLOR1, -0x00400900, +NV10_PGRAPH_CTX_USER, +NV04_PGRAPH_DMA_START_0, +NV04_PGRAPH_DMA_START_1, +NV04_PGRAPH_DMA_LENGTH, +NV04_PGRAPH_DMA_MISC, +NV10_PGRAPH_DMA_PITCH, +NV04_PGRAPH_BOFFSET0, +NV04_PGRAPH_BBASE0, +NV04_PGRAPH_BLIMIT0, +NV04_PGRAPH_BOFFSET1, +NV04_PGRAPH_BBASE1, +NV04_PGRAPH_BLIMIT1, +NV04_PGRAPH_BOFFSET2, +NV04_PGRAPH_BBASE2, +NV04_PGRAPH_BLIMIT2, +NV04_PGRAPH_BOFFSET3, +NV04_PGRAPH_BBASE3, +NV04_PGRAPH_BLIMIT3, +NV04_PGRAPH_BOFFSET4, +NV04_PGRAPH_BBASE4, +NV04_PGRAPH_BLIMIT4, +NV04_PGRAPH_BOFFSET5, +NV04_PGRAPH_BBASE5, +NV04_PGRAPH_BLIMIT5, +NV04_PGRAPH_BPITCH0, +NV04_PGRAPH_BPITCH1, +NV04_PGRAPH_BPITCH2, +NV04_PGRAPH_BPITCH3, +NV04_PGRAPH_BPITCH4, +NV10_PGRAPH_SURFACE, +NV10_PGRAPH_STATE, +NV04_PGRAPH_BSWIZZLE2, +NV04_PGRAPH_BSWIZZLE5, +NV04_PGRAPH_BPIXEL, +NV10_PGRAPH_NOTIFY, +NV04_PGRAPH_PATT_COLOR0, +NV04_PGRAPH_PATT_COLOR1, +NV04_PGRAPH_PATT_COLORRAM, /* 64 values from 0x400900 to 0x4009fc */ 0x00400904, 0x00400908, 0x0040090c, @@ -334,14 +332,14 @@ NV_PGRAPH_PATT_COLOR1, 0x004009f4, 0x004009f8, 0x004009fc, -0x00400808, +NV04_PGRAPH_PATTERN, /* 2 values from 0x400808 to 0x40080c */ 0x0040080c, -NV_PGRAPH_PATTERN_SHAPE, -NV_PGRAPH_MONO_COLOR0, -NV_PGRAPH_ROP3, -NV_PGRAPH_CHROMA, -NV_PGRAPH_BETA_AND, -NV_PGRAPH_BETA_PREMULT, +NV04_PGRAPH_PATTERN_SHAPE, +NV03_PGRAPH_MONO_COLOR0, +NV04_PGRAPH_ROP3, +NV04_PGRAPH_CHROMA, +NV04_PGRAPH_BETA_AND, +NV04_PGRAPH_BETA_PREMULT, 0x00400e70, 0x00400e74, 0x00400e78, @@ -353,28 +351,12 @@ NV_PGRAPH_BETA_PREMULT, 0x00400ea0, 0x00400ea4, 0x00400ea8, -0x00400eac, -0x00400eb0, -0x00400eb4, -0x00400eb8, -0x00400ebc, -0x00400ec0, -0x00400ec4, -0x00400ec8, -0x00400ecc, -0x00400ed0, -0x00400ed4, -0x00400ed8, -0x00400edc, -0x00400ee0, -0x00400a00, -0x00400a04, 0x00400e90, 0x00400e94, 0x00400e98, 0x00400e9c, -0x00400f00, -0x00400f20, +NV10_PGRAPH_WINDOWCLIP_HORIZONTAL, /* 8 values from 0x400f00 to 0x400f1c */ +NV10_PGRAPH_WINDOWCLIP_VERTICAL, /* 8 values from 0x400f20 to 0x400f3c */ 0x00400f04, 0x00400f24, 0x00400f08, @@ -389,14 +371,14 @@ NV_PGRAPH_BETA_PREMULT, 0x00400f38, 0x00400f1c, 0x00400f3c, -NV_PGRAPH_XFMODE0, -NV_PGRAPH_XFMODE1, -NV_PGRAPH_GLOBALSTATE0, -NV_PGRAPH_GLOBALSTATE1, -NV_PGRAPH_STORED_FMT, -NV_PGRAPH_SOURCE_COLOR, -0x00400400, -0x00400480, +NV10_PGRAPH_XFMODE0, +NV10_PGRAPH_XFMODE1, +NV10_PGRAPH_GLOBALSTATE0, +NV10_PGRAPH_GLOBALSTATE1, +NV04_PGRAPH_STORED_FMT, +NV04_PGRAPH_SOURCE_COLOR, +NV03_PGRAPH_ABS_X_RAM, /* 32 values from 0x400400 to 0x40047c */ +NV03_PGRAPH_ABS_Y_RAM, /* 32 values from 0x400480 to 0x4004fc */ 0x00400404, 0x00400484, 0x00400408, @@ -459,27 +441,27 @@ NV_PGRAPH_SOURCE_COLOR, 0x004004f8, 0x0040047c, 0x004004fc, -NV_PGRAPH_ABS_UCLIP_XMIN, -NV_PGRAPH_ABS_UCLIP_XMAX, -NV_PGRAPH_ABS_UCLIP_YMIN, -NV_PGRAPH_ABS_UCLIP_YMAX, +NV03_PGRAPH_ABS_UCLIP_XMIN, +NV03_PGRAPH_ABS_UCLIP_XMAX, +NV03_PGRAPH_ABS_UCLIP_YMIN, +NV03_PGRAPH_ABS_UCLIP_YMAX, 0x00400550, 0x00400558, 0x00400554, 0x0040055c, -NV_PGRAPH_ABS_UCLIPA_XMIN, -NV_PGRAPH_ABS_UCLIPA_XMAX, -NV_PGRAPH_ABS_UCLIPA_YMIN, -NV_PGRAPH_ABS_UCLIPA_YMAX, -NV_PGRAPH_ABS_ICLIP_XMAX, -NV_PGRAPH_ABS_ICLIP_YMAX, -NV_PGRAPH_XY_LOGIC_MISC1, -NV_PGRAPH_XY_LOGIC_MISC2, -NV_PGRAPH_XY_LOGIC_MISC3, -NV_PGRAPH_CLIPX_0, -NV_PGRAPH_CLIPX_1, -NV_PGRAPH_CLIPY_0, -NV_PGRAPH_CLIPY_1, +NV03_PGRAPH_ABS_UCLIPA_XMIN, +NV03_PGRAPH_ABS_UCLIPA_XMAX, +NV03_PGRAPH_ABS_UCLIPA_YMIN, +NV03_PGRAPH_ABS_UCLIPA_YMAX, +NV03_PGRAPH_ABS_ICLIP_XMAX, +NV03_PGRAPH_ABS_ICLIP_YMAX, +NV03_PGRAPH_XY_LOGIC_MISC1, +NV03_PGRAPH_XY_LOGIC_MISC2, +NV03_PGRAPH_XY_LOGIC_MISC3, +NV03_PGRAPH_CLIPX_0, +NV03_PGRAPH_CLIPX_1, +NV03_PGRAPH_CLIPY_0, +NV03_PGRAPH_CLIPY_1, 0x00400e40, 0x00400e44, 0x00400e48, @@ -508,34 +490,54 @@ NV_PGRAPH_CLIPY_1, 0x00400e34, 0x00400e38, 0x00400e3c, -NV_PGRAPH_PASSTHRU_0, -NV_PGRAPH_PASSTHRU_1, -NV_PGRAPH_PASSTHRU_2, -NV_PGRAPH_DIMX_TEXTURE, -NV_PGRAPH_WDIMX_TEXTURE, -NV_PGRAPH_DVD_COLORFMT, -NV_PGRAPH_SCALED_FORMAT, -NV_PGRAPH_MISC24_0, -NV_PGRAPH_MISC24_1, -NV_PGRAPH_MISC24_2, -NV_PGRAPH_X_MISC, -NV_PGRAPH_Y_MISC, -NV_PGRAPH_VALID1, -NV_PGRAPH_VALID2, -0 +NV04_PGRAPH_PASSTHRU_0, +NV04_PGRAPH_PASSTHRU_1, +NV04_PGRAPH_PASSTHRU_2, +NV10_PGRAPH_DIMX_TEXTURE, +NV10_PGRAPH_WDIMX_TEXTURE, +NV10_PGRAPH_DVD_COLORFMT, +NV10_PGRAPH_SCALED_FORMAT, +NV04_PGRAPH_MISC24_0, +NV04_PGRAPH_MISC24_1, +NV04_PGRAPH_MISC24_2, +NV03_PGRAPH_X_MISC, +NV03_PGRAPH_Y_MISC, +NV04_PGRAPH_VALID1, +NV04_PGRAPH_VALID2, +}; + +static int nv17_graph_ctx_regs [] = { +NV10_PGRAPH_DEBUG_4, +0x004006b0, +0x00400eac, +0x00400eb0, +0x00400eb4, +0x00400eb8, +0x00400ebc, +0x00400ec0, +0x00400ec4, +0x00400ec8, +0x00400ecc, +0x00400ed0, +0x00400ed4, +0x00400ed8, +0x00400edc, +0x00400ee0, +0x00400a00, +0x00400a04, }; void nouveau_nv10_context_switch(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = dev->dev_private; - int channel, channel_old, i; + int channel, channel_old, i, j; - channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1); - channel_old = (NV_READ(NV_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); + channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); + channel_old = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel); - NV_WRITE(NV_PGRAPH_FIFO,0x0); + NV_WRITE(NV04_PGRAPH_FIFO,0x0); #if 0 NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000); NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000000); @@ -543,52 +545,65 @@ void nouveau_nv10_context_switch(drm_device_t *dev) #endif // save PGRAPH context - for (i = 0; nv10_graph_ctx_regs[i]; i++) - dev_priv->fifos[channel_old].nv10_pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); + for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) + dev_priv->fifos[channel_old].pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); + if (dev_priv->chipset>=0x17) { + for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) + dev_priv->fifos[channel_old].pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]); + } nouveau_wait_for_idle(dev); - NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10000000); - NV_WRITE(NV_PGRAPH_CTX_USER, (NV_READ(NV_PGRAPH_CTX_USER) & 0xffffff) | (0x1f << 24)); + NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10000000); + NV_WRITE(NV10_PGRAPH_CTX_USER, (NV_READ(NV10_PGRAPH_CTX_USER) & 0xffffff) | (0x1f << 24)); nouveau_wait_for_idle(dev); // restore PGRAPH context //XXX not working yet -#if 0 - for (i = 0; nv10_graph_ctx_regs[i]; i++) - NV_WRITE(nv10_graph_ctx_regs[i], dev_priv->fifos[channel].nv10_pgraph_ctx[i]); +#if 1 + for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) + NV_WRITE(nv10_graph_ctx_regs[i], dev_priv->fifos[channel].pgraph_ctx[i]); + if (dev_priv->chipset>=0x17) { + for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) + NV_WRITE(nv17_graph_ctx_regs[j], dev_priv->fifos[channel].pgraph_ctx[i]); + } nouveau_wait_for_idle(dev); #endif - NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10010100); - NV_WRITE(NV_PGRAPH_CTX_USER, channel << 24); - NV_WRITE(NV_PGRAPH_FFINTFC_ST2, NV_READ(NV_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); + NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10010100); + NV_WRITE(NV10_PGRAPH_CTX_USER, channel << 24); + NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); #if 0 NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001); NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001); NV_WRITE(NV_PFIFO_CACHES, 0x00000001); #endif - NV_WRITE(NV_PGRAPH_FIFO,0x1); + NV_WRITE(NV04_PGRAPH_FIFO,0x1); } int nv10_graph_context_create(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; DRM_DEBUG("nv10_graph_context_create %d\n", channel); - memset(dev_priv->fifos[channel].nv10_pgraph_ctx, 0, sizeof(dev_priv->fifos[channel].nv10_pgraph_ctx)); + memset(dev_priv->fifos[channel].pgraph_ctx, 0, sizeof(dev_priv->fifos[channel].pgraph_ctx)); //dev_priv->fifos[channel].pgraph_ctx_user = channel << 24; - dev_priv->fifos[channel].nv10_pgraph_ctx[0] = 0x0001ffff; + dev_priv->fifos[channel].pgraph_ctx[0] = 0x0001ffff; /* is it really needed ??? */ - dev_priv->fifos[channel].nv10_pgraph_ctx[1] = NV_READ(NV_PGRAPH_DEBUG_4); - dev_priv->fifos[channel].nv10_pgraph_ctx[2] = NV_READ(0x004006b0); + if (dev_priv->chipset>=0x17) { + dev_priv->fifos[channel].pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 0] = NV_READ(NV10_PGRAPH_DEBUG_4); + dev_priv->fifos[channel].pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 1] = NV_READ(0x004006b0); + } + + + //XXX should be saved/restored for each fifo + //we supposed here we have X fifo and only one 3D fifo. + nv10_praph_pipe(dev); return 0; } int nv10_graph_init(drm_device_t *dev) { - //XXX should be call at each fifo init - nv10_praph_pipe(dev); return 0; } diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index 6e351a2d..9ba6a873 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -56,9 +56,9 @@ static void nv20_graph_rdi(drm_device_t *dev) { (drm_nouveau_private_t *)dev->dev_private; int i; - NV_WRITE(NV_PGRAPH_RDI_INDEX, 0x2c80000); + NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x2c80000); for (i = 0; i < 32; i++) - NV_WRITE(NV_PGRAPH_RDI_DATA, 0); + NV_WRITE(NV10_PGRAPH_RDI_DATA, 0); nouveau_wait_for_idle(dev); } @@ -77,8 +77,8 @@ static void nv20_graph_context_save_current(drm_device_t *dev, int channel) { if (instance != nouveau_chip_instance_get(dev, dev_priv->fifos[channel].ramin_grctx)) DRM_ERROR("nv20_graph_context_save_current : bad instance\n"); - NV_WRITE(NV_PGRAPH_CHANNEL_CTX_SIZE, instance); - NV_WRITE(NV_PGRAPH_CHANNEL_CTX_POINTER, 2 /* save ctx */); + NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, instance); + NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_POINTER, 2 /* save ctx */); } @@ -96,9 +96,9 @@ static void nv20_graph_context_restore(drm_device_t *dev, int channel) { if (instance != nouveau_chip_instance_get(dev, dev_priv->fifos[channel].ramin_grctx)) DRM_ERROR("nv20_graph_context_restore_current : bad instance\n"); - NV_WRITE(NV_PGRAPH_CTX_USER, channel << 24); - NV_WRITE(NV_PGRAPH_CHANNEL_CTX_SIZE, instance); - NV_WRITE(NV_PGRAPH_CHANNEL_CTX_POINTER, 1 /* restore ctx */); + NV_WRITE(NV10_PGRAPH_CTX_USER, channel << 24); + NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, instance); + NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_POINTER, 1 /* restore ctx */); } void nouveau_nv20_context_switch(drm_device_t *dev) @@ -106,30 +106,30 @@ void nouveau_nv20_context_switch(drm_device_t *dev) drm_nouveau_private_t *dev_priv = dev->dev_private; int channel, channel_old; - channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1); - channel_old = (NV_READ(NV_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); + channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); + channel_old = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel); - NV_WRITE(NV_PGRAPH_FIFO,0x0); + NV_WRITE(NV04_PGRAPH_FIFO,0x0); nv20_graph_context_save_current(dev, channel_old); nouveau_wait_for_idle(dev); - NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10000000); + NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10000000); nv20_graph_context_restore(dev, channel); nouveau_wait_for_idle(dev); - if ((NV_READ(NV_PGRAPH_CTX_USER) >> 24) != channel) - DRM_ERROR("nouveau_nv20_context_switch : wrong channel restored %x %x!!!\n", channel, NV_READ(NV_PGRAPH_CTX_USER) >> 24); + if ((NV_READ(NV10_PGRAPH_CTX_USER) >> 24) != channel) + DRM_ERROR("nouveau_nv20_context_switch : wrong channel restored %x %x!!!\n", channel, NV_READ(NV10_PGRAPH_CTX_USER) >> 24); - NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10010100); - NV_WRITE(NV_PGRAPH_FFINTFC_ST2, NV_READ(NV_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); + NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10010100); + NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); - NV_WRITE(NV_PGRAPH_FIFO,0x1); + NV_WRITE(NV04_PGRAPH_FIFO,0x1); } int nv20_graph_init(drm_device_t *dev) { @@ -146,7 +146,7 @@ int nv20_graph_init(drm_device_t *dev) { for (i=0; i< dev_priv->ctx_table_size; i+=4) INSTANCE_WR(dev_priv->ctx_table, i/4, 0x00000000); - NV_WRITE(NV_PGRAPH_CHANNEL_CTX_TABLE, nouveau_chip_instance_get(dev, dev_priv->ctx_table)); + NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, nouveau_chip_instance_get(dev, dev_priv->ctx_table)); //XXX need to be done and save/restore for each fifo ??? nv20_graph_rdi(dev); diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c index a5f01ea5..cb183bea 100644 --- a/shared-core/nv30_graph.c +++ b/shared-core/nv30_graph.c @@ -107,10 +107,9 @@ int nv30_graph_context_create(drm_device_t *dev, int channel) struct nouveau_fifo *chan = &dev_priv->fifos[channel]; void (*ctx_init)(drm_device_t *, struct mem_block *); unsigned int ctx_size; - int i, chipset; + int i; - chipset = (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000) >> 20; - switch (chipset) { + switch (dev_priv->chipset) { default: ctx_size = NV30_GRCTX_SIZE; ctx_init = nv30_graph_context_init; @@ -137,10 +136,7 @@ int nv30_graph_init(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; - int i, chipset; - - chipset = (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000) >> 20; - DRM_DEBUG("chipset (from PMC_BOOT_0): NV%02X\n", chipset); + int i; /* Create Context Pointer Table */ dev_priv->ctx_table_size = 32 * 4; @@ -151,7 +147,7 @@ int nv30_graph_init(drm_device_t *dev) for (i=0; i< dev_priv->ctx_table_size; i+=4) INSTANCE_WR(dev_priv->ctx_table, i/4, 0x00000000); - NV_WRITE(NV_PGRAPH_CHANNEL_CTX_TABLE, nouveau_chip_instance_get(dev, dev_priv->ctx_table)); + NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, nouveau_chip_instance_get(dev, dev_priv->ctx_table)); return 0; } diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c index 00583cdc..659767f2 100644 --- a/shared-core/nv40_graph.c +++ b/shared-core/nv40_graph.c @@ -611,10 +611,9 @@ nv40_graph_context_create(drm_device_t *dev, int channel) struct nouveau_fifo *chan = &dev_priv->fifos[channel]; void (*ctx_init)(drm_device_t *, struct mem_block *); unsigned int ctx_size; - int i, chipset; + int i; - chipset = (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000) >> 20; - switch (chipset) { + switch (dev_priv->chipset) { case 0x40: ctx_size = NV40_GRCTX_SIZE; ctx_init = nv40_graph_context_init; @@ -665,11 +664,11 @@ nv40_graph_context_save_current(drm_device_t *dev) uint32_t instance; int i; - NV_WRITE(NV_PGRAPH_FIFO, 0); + NV_WRITE(NV04_PGRAPH_FIFO, 0); instance = NV_READ(0x40032C) & 0xFFFFF; if (!instance) { - NV_WRITE(NV_PGRAPH_FIFO, 1); + NV_WRITE(NV04_PGRAPH_FIFO, 1); return; } @@ -685,11 +684,11 @@ nv40_graph_context_save_current(drm_device_t *dev) DRM_ERROR("failed to save current grctx to ramin\n"); DRM_ERROR("instance = 0x%08x\n", NV_READ(0x40032C)); DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(0x40030C)); - NV_WRITE(NV_PGRAPH_FIFO, 1); + NV_WRITE(NV04_PGRAPH_FIFO, 1); return; } - NV_WRITE(NV_PGRAPH_FIFO, 1); + NV_WRITE(NV04_PGRAPH_FIFO, 1); } /* Restore the context for a specific channel into PGRAPH @@ -706,7 +705,7 @@ nv40_graph_context_restore(drm_device_t *dev, int channel) instance = nouveau_chip_instance_get(dev, chan->ramin_grctx); - NV_WRITE(NV_PGRAPH_FIFO, 0); + NV_WRITE(NV04_PGRAPH_FIFO, 0); NV_WRITE(0x400784, instance); NV_WRITE(0x400310, NV_READ(0x400310) | 0x40); NV_WRITE(0x400304, 1); @@ -720,7 +719,7 @@ nv40_graph_context_restore(drm_device_t *dev, int channel) channel); DRM_ERROR("instance = 0x%08x\n", instance); DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(0x40030C)); - NV_WRITE(NV_PGRAPH_FIFO, 1); + NV_WRITE(NV04_PGRAPH_FIFO, 1); return; } @@ -736,7 +735,7 @@ nv40_graph_context_restore(drm_device_t *dev, int channel) * recieve PGRAPH_INTR_CONTEXT_SWITCH */ NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE, instance); - NV_WRITE(NV_PGRAPH_FIFO, 1); + NV_WRITE(NV04_PGRAPH_FIFO, 1); } /* Some voodoo that makes context switching work without the binary driver @@ -896,17 +895,16 @@ nv40_graph_init(drm_device_t *dev) (drm_nouveau_private_t *)dev->dev_private; uint32_t *ctx_voodoo; uint32_t pg0220_inst; - int i, chipset; + int i; - chipset = (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000) >> 20; - DRM_DEBUG("chipset (from PMC_BOOT_0): NV%02X\n", chipset); - switch (chipset) { + switch (dev_priv->chipset) { case 0x40: ctx_voodoo = nv40_ctx_voodoo; break; case 0x43: ctx_voodoo = nv43_ctx_voodoo; break; case 0x4a: ctx_voodoo = nv4a_ctx_voodoo; break; case 0x4e: ctx_voodoo = nv4e_ctx_voodoo; break; default: - DRM_ERROR("Unknown ctx_voodoo for chipset 0x%02x\n", chipset); + DRM_ERROR("Unknown ctx_voodoo for chipset 0x%02x\n", + dev_priv->chipset); ctx_voodoo = NULL; break; } @@ -932,7 +930,7 @@ nv40_graph_init(drm_device_t *dev) NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM); pg0220_inst = nouveau_chip_instance_get(dev, dev_priv->fb_obj->instance); - NV_WRITE(NV_PGRAPH_NV40_UNK220, pg0220_inst); + NV_WRITE(NV40_PGRAPH_UNK220, pg0220_inst); return 0; } diff --git a/shared-core/via_dma.c b/shared-core/via_dma.c index 90dbb6a2..09159634 100644 --- a/shared-core/via_dma.c +++ b/shared-core/via_dma.c @@ -192,6 +192,11 @@ static int via_initialize(drm_device_t * dev, return DRM_ERR(EFAULT); } + if (dev_priv->chipset == VIA_DX9_0) { + DRM_ERROR("AGP DMA is not supported on this chip\n"); + return DRM_ERR(EINVAL); + } + dev_priv->ring.map.offset = dev->agp->base + init->offset; dev_priv->ring.map.size = init->size; dev_priv->ring.map.type = 0; @@ -294,7 +299,7 @@ static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd) cmd->size, dev, 1))) { return ret; } - + vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size); if (vb == NULL) { return DRM_ERR(EAGAIN); @@ -428,70 +433,46 @@ static inline uint32_t *via_get_dma(drm_via_private_t * dev_priv) * modifying the pause address stored in the buffer itself. If * the regulator has already paused, restart it. */ + static int via_hook_segment(drm_via_private_t *dev_priv, uint32_t pause_addr_hi, uint32_t pause_addr_lo, int no_pci_fire) { int paused, count; volatile uint32_t *paused_at = dev_priv->last_pause_ptr; + uint32_t reader,ptr; + paused = 0; via_flush_write_combine(); - while(! *(via_get_dma(dev_priv)-1)); *dev_priv->last_pause_ptr = pause_addr_lo; via_flush_write_combine(); - - /* - * The below statement is inserted to really force the flush. - * Not sure it is needed. - */ - - while(! *dev_priv->last_pause_ptr); + reader = *(dev_priv->hw_addr_ptr); + ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) + + dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4; dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1; - while(! *dev_priv->last_pause_ptr); - - paused = 0; - count = 20; - - while (!(paused = (VIA_READ(0x41c) & 0x80000000)) && count--); - if ((count <= 8) && (count >= 0)) { - uint32_t rgtr, ptr; - rgtr = *(dev_priv->hw_addr_ptr); - ptr = ((volatile char *)dev_priv->last_pause_ptr - - dev_priv->dma_ptr) + dev_priv->dma_offset + - (uint32_t) dev_priv->agpAddr + 4 - CMDBUF_ALIGNMENT_SIZE; - if (rgtr <= ptr) { - DRM_ERROR - ("Command regulator\npaused at count %d, address %x, " - "while current pause address is %x.\n" - "Please mail this message to " - "<unichrome-devel@lists.sourceforge.net>\n", count, - rgtr, ptr); - } + if ((ptr - reader) <= dev_priv->dma_diff ) { + count = 10000000; + while (!(paused = (VIA_READ(0x41c) & 0x80000000)) && count--); } - + if (paused && !no_pci_fire) { - uint32_t rgtr,ptr; - uint32_t ptr_low; - - count = 1000000; - while ((VIA_READ(VIA_REG_STATUS) & VIA_CMD_RGTR_BUSY) - && count--); - - rgtr = *(dev_priv->hw_addr_ptr); - ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) + - dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4; - - - ptr_low = (ptr > 3*CMDBUF_ALIGNMENT_SIZE) ? - ptr - 3*CMDBUF_ALIGNMENT_SIZE : 0; - if (rgtr <= ptr && rgtr >= ptr_low) { + reader = *(dev_priv->hw_addr_ptr); + if ((ptr - reader) == dev_priv->dma_diff) { + + /* + * There is a concern that these writes may stall the PCI bus + * if the GPU is not idle. However, idling the GPU first + * doesn't make a difference. + */ + VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16)); VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi); VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo); VIA_READ(VIA_REG_TRANSPACE); - } + } } + return paused; } @@ -500,6 +481,9 @@ static int via_hook_segment(drm_via_private_t *dev_priv, static int via_wait_idle(drm_via_private_t * dev_priv) { int count = 10000000; + + while (!(VIA_READ(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && count--); + while (count-- && (VIA_READ(VIA_REG_STATUS) & (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY))) ; @@ -546,7 +530,9 @@ static void via_cmdbuf_start(drm_via_private_t * dev_priv) uint32_t end_addr, end_addr_lo; uint32_t command; uint32_t agp_base; - + uint32_t ptr; + uint32_t reader; + int count; dev_priv->dma_low = 0; @@ -576,6 +562,24 @@ static void via_cmdbuf_start(drm_via_private_t * dev_priv) DRM_WRITEMEMORYBARRIER(); VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK); VIA_READ(VIA_REG_TRANSPACE); + + dev_priv->dma_diff = 0; + + count = 10000000; + while (!(VIA_READ(0x41c) & 0x80000000) && count--); + + reader = *(dev_priv->hw_addr_ptr); + ptr = ((volatile char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) + + dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4; + + /* + * This is the difference between where we tell the + * command reader to pause and where it actually pauses. + * This differs between hw implementation so we need to + * detect it. + */ + + dev_priv->dma_diff = ptr - reader; } static void via_pad_cache(drm_via_private_t *dev_priv, int qwords) @@ -593,20 +597,18 @@ static inline void via_dummy_bitblt(drm_via_private_t * dev_priv) uint32_t *vb = via_get_dma(dev_priv); SetReg2DAGP(0x0C, (0 | (0 << 16))); SetReg2DAGP(0x10, 0 | (0 << 16)); - SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000); + SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000); } - static void via_cmdbuf_jump(drm_via_private_t * dev_priv) { uint32_t agp_base; uint32_t pause_addr_lo, pause_addr_hi; uint32_t jump_addr_lo, jump_addr_hi; volatile uint32_t *last_pause_ptr; - uint32_t dma_low_save1, dma_low_save2; agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; - via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi, + via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi, &jump_addr_lo, 0); dev_priv->dma_wrap = dev_priv->dma_low; @@ -622,38 +624,14 @@ static void via_cmdbuf_jump(drm_via_private_t * dev_priv) } via_dummy_bitblt(dev_priv); - via_dummy_bitblt(dev_priv); - - last_pause_ptr = - via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, - &pause_addr_lo, 0) -1; - via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, - &pause_addr_lo, 0); - - *last_pause_ptr = pause_addr_lo; - dma_low_save1 = dev_priv->dma_low; - - /* - * Now, set a trap that will pause the regulator if it tries to rerun the old - * command buffer. (Which may happen if via_hook_segment detecs a command regulator pause - * and reissues the jump command over PCI, while the regulator has already taken the jump - * and actually paused at the current buffer end). - * There appears to be no other way to detect this condition, since the hw_addr_pointer - * does not seem to get updated immediately when a jump occurs. - */ - - last_pause_ptr = - via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, + via_dummy_bitblt(dev_priv); + last_pause_ptr = via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, &pause_addr_lo, 0) -1; - via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, + via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, &pause_addr_lo, 0); *last_pause_ptr = pause_addr_lo; - dma_low_save2 = dev_priv->dma_low; - dev_priv->dma_low = dma_low_save1; via_hook_segment( dev_priv, jump_addr_hi, jump_addr_lo, 0); - dev_priv->dma_low = dma_low_save2; - via_hook_segment( dev_priv, pause_addr_hi, pause_addr_lo, 0); } diff --git a/shared-core/via_drm.h b/shared-core/via_drm.h index 16421d74..88345bdf 100644 --- a/shared-core/via_drm.h +++ b/shared-core/via_drm.h @@ -42,11 +42,11 @@ * backwards incompatibilities, (which should be avoided whenever possible). */ -#define VIA_DRM_DRIVER_DATE "20061227" +#define VIA_DRM_DRIVER_DATE "20070202" #define VIA_DRM_DRIVER_MAJOR 2 #define VIA_DRM_DRIVER_MINOR 11 -#define VIA_DRM_DRIVER_PATCHLEVEL 0 +#define VIA_DRM_DRIVER_PATCHLEVEL 1 #define VIA_DRM_DRIVER_VERSION (((VIA_DRM_DRIVER_MAJOR) << 16) | (VIA_DRM_DRIVER_MINOR)) #define VIA_NR_SAREA_CLIPRECTS 8 diff --git a/shared-core/via_drv.h b/shared-core/via_drv.h index 7a8f2c34..42d0c749 100644 --- a/shared-core/via_drv.h +++ b/shared-core/via_drv.h @@ -102,6 +102,7 @@ typedef struct drm_via_private { #ifdef VIA_HAVE_DMABLIT drm_via_blitq_t blit_queues[VIA_NUM_BLIT_ENGINES]; #endif + uint32_t dma_diff; } drm_via_private_t; enum via_family { |