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-rw-r--r--shared-core/radeon_cp.c26
-rw-r--r--shared-core/savage_bci.c34
2 files changed, 37 insertions, 23 deletions
diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c
index 9eaa2d76..4606a332 100644
--- a/shared-core/radeon_cp.c
+++ b/shared-core/radeon_cp.c
@@ -2006,7 +2006,9 @@ int radeon_cp_buffers(DRM_IOCTL_ARGS)
/* Always create a map record for MMIO and FB memory, done from DRIVER_POSTINIT */
int radeon_preinit(struct drm_device *dev, unsigned long flags)
{
+#if defined(__linux__)
u32 save, temp;
+#endif
drm_radeon_private_t *dev_priv;
int ret = 0;
@@ -2030,19 +2032,18 @@ int radeon_preinit(struct drm_device *dev, unsigned long flags)
break;
}
-#ifdef __linux__
- /* registers */
- if ((ret = drm_initmap(dev, pci_resource_start(dev->pdev, 2),
- pci_resource_len(dev->pdev, 2), _DRM_REGISTERS,
- 0)))
+ ret = drm_initmap(dev, drm_get_resource_start(dev, 2),
+ drm_get_resource_len(dev, 2), 2, _DRM_REGISTERS, 0);
+ if (ret != 0)
return ret;
- /* framebuffer */
- if ((ret = drm_initmap(dev, pci_resource_start(dev->pdev, 0),
- pci_resource_len(dev->pdev, 0),
- _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING)))
+ ret = drm_initmap(dev, drm_get_resource_start(dev, 0),
+ drm_get_resource_len(dev, 0), 0, _DRM_FRAME_BUFFER,
+ _DRM_WRITE_COMBINING);
+ if (ret != 0)
return ret;
+#if defined(__linux__)
/* There are signatures in BIOS and PCI-SSID for a PCI card, but they are not very reliable.
Following detection method works for all cards tested so far.
Note, checking AGP_ENABLE bit after drmAgpEnable call can also give the correct result.
@@ -2057,9 +2058,14 @@ int radeon_preinit(struct drm_device *dev, unsigned long flags)
if (temp & RADEON_AGP_ENABLE)
dev_priv->flags |= CHIP_IS_AGP;
#else
+ /* The above method of detecting AGP is known to not work correctly,
+ * according to Mike Harris. The solution is to walk the capabilities
+ * list, which should be done in drm_device_is_agp().
+ */
if (drm_device_is_agp(dev))
- dev_priv->flags & CHIP_IS_AGP;
+ dev_priv->flags |= CHIP_IS_AGP;
#endif
+
DRM_DEBUG("%s card detected\n",
((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : "PCI"));
diff --git a/shared-core/savage_bci.c b/shared-core/savage_bci.c
index 4656a902..36fb8737 100644
--- a/shared-core/savage_bci.c
+++ b/shared-core/savage_bci.c
@@ -296,6 +296,7 @@ int savage_preinit(drm_device_t *dev, unsigned long chipset)
{
drm_savage_private_t *dev_priv;
unsigned long mmio_base, fb_base, fb_size, aperture_base;
+ unsigned int fb_rsrc, aper_rsrc;
int ret = 0;
dev_priv = drm_alloc(sizeof(drm_savage_private_t), DRM_MEM_DRIVER);
@@ -310,12 +311,14 @@ int savage_preinit(drm_device_t *dev, unsigned long chipset)
dev_priv->mtrr[1].handle = -1;
dev_priv->mtrr[2].handle = -1;
if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
- fb_base = pci_resource_start(dev->pdev, 0);
+ fb_rsrc = 0;
+ fb_base = drm_get_resource_start(dev, 0);
fb_size = SAVAGE_FB_SIZE_S3;
mmio_base = fb_base + SAVAGE_FB_SIZE_S3;
+ aper_rsrc = 0;
aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
/* this should always be true */
- if (pci_resource_len(dev->pdev, 0) == 0x08000000) {
+ if (drm_get_resource_len(dev, 0) == 0x08000000) {
/* Don't make MMIO write-cobining! We need 3
* MTRRs. */
dev_priv->mtrr[0].base = fb_base;
@@ -335,15 +338,17 @@ int savage_preinit(drm_device_t *dev, unsigned long chipset)
MTRR_TYPE_WRCOMB, 1);
} else {
DRM_ERROR("strange pci_resource_len %08lx\n",
- pci_resource_len(dev->pdev, 0));
+ drm_get_resource_len(dev, 0));
}
} else if (chipset != S3_SUPERSAVAGE && chipset != S3_SAVAGE2000) {
- mmio_base = pci_resource_start(dev->pdev, 0);
- fb_base = pci_resource_start(dev->pdev, 1);
+ mmio_base = drm_get_resource_start(dev, 0);
+ fb_rsrc = 1;
+ fb_base = drm_get_resource_start(dev, 1);
fb_size = SAVAGE_FB_SIZE_S4;
+ aper_rsrc = 1;
aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
/* this should always be true */
- if (pci_resource_len(dev->pdev, 1) == 0x08000000) {
+ if (drm_get_resource_len(dev, 1) == 0x08000000) {
/* Can use one MTRR to cover both fb and
* aperture. */
dev_priv->mtrr[0].base = fb_base;
@@ -353,29 +358,32 @@ int savage_preinit(drm_device_t *dev, unsigned long chipset)
MTRR_TYPE_WRCOMB, 1);
} else {
DRM_ERROR("strange pci_resource_len %08lx\n",
- pci_resource_len(dev->pdev, 1));
+ drm_get_resource_len(dev, 1));
}
} else {
- mmio_base = pci_resource_start(dev->pdev, 0);
- fb_base = pci_resource_start(dev->pdev, 1);
- fb_size = pci_resource_len(dev->pdev, 1);
- aperture_base = pci_resource_start(dev->pdev, 2);
+ mmio_base = drm_get_resource_start(dev, 0);
+ fb_rsrc = 1;
+ fb_base = drm_get_resource_start(dev, 1);
+ fb_size = drm_get_resource_len(dev, 1);
+ aper_rsrc = 2;
+ aperture_base = drm_get_resource_start(dev, 2);
/* Automatic MTRR setup will do the right thing. */
}
- if ((ret = drm_initmap(dev, mmio_base, SAVAGE_MMIO_SIZE,
+ if ((ret = drm_initmap(dev, mmio_base, SAVAGE_MMIO_SIZE, 0,
_DRM_REGISTERS, 0)))
return ret;
if (!(dev_priv->mmio = drm_core_findmap (dev, mmio_base)))
return DRM_ERR(ENOMEM);
- if ((ret = drm_initmap(dev, fb_base, fb_size,
+ if ((ret = drm_initmap(dev, fb_base, fb_size, fb_rsrc,
_DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING)))
return ret;
if (!(dev_priv->fb = drm_core_findmap (dev, fb_base)))
return DRM_ERR(ENOMEM);
if ((ret = drm_initmap(dev, aperture_base, SAVAGE_APERTURE_SIZE,
+ aper_rsrc,
_DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING)))
return ret;
if (!(dev_priv->aperture = drm_core_findmap (dev, aperture_base)))
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 05:50:53 +0000