diff options
Diffstat (limited to 'shared-core')
| -rw-r--r-- | shared-core/nouveau_drm.h | 120 |
1 files changed, 18 insertions, 102 deletions
diff --git a/shared-core/nouveau_drm.h b/shared-core/nouveau_drm.h index dc6a1945..3e52b245 100644 --- a/shared-core/nouveau_drm.h +++ b/shared-core/nouveau_drm.h @@ -25,7 +25,7 @@ #ifndef __NOUVEAU_DRM_H__ #define __NOUVEAU_DRM_H__ -#define NOUVEAU_DRM_HEADER_PATCHLEVEL 14 +#define NOUVEAU_DRM_HEADER_PATCHLEVEL 15 struct drm_nouveau_channel_alloc { uint32_t fb_ctxdma_handle; @@ -34,8 +34,7 @@ struct drm_nouveau_channel_alloc { int channel; /* Notifier memory */ - drm_handle_t notifier; - int notifier_size; + uint32_t notifier_handle; /* DRM-enforced subchannel assignments */ struct { @@ -43,15 +42,6 @@ struct drm_nouveau_channel_alloc { uint32_t grclass; } subchan[8]; uint32_t nr_subchan; - -/* !MM_ENABLED ONLY */ - uint32_t put_base; - /* FIFO control regs */ - drm_handle_t ctrl; - int ctrl_size; - /* DMA command buffer */ - drm_handle_t cmdbuf; - int cmdbuf_size; }; struct drm_nouveau_channel_free { @@ -64,14 +54,10 @@ struct drm_nouveau_grobj_alloc { int class; }; -#define NOUVEAU_MEM_ACCESS_RO 1 -#define NOUVEAU_MEM_ACCESS_WO 2 -#define NOUVEAU_MEM_ACCESS_RW 3 struct drm_nouveau_notifierobj_alloc { - int channel; + uint32_t channel; uint32_t handle; - int count; - + uint32_t size; uint32_t offset; }; @@ -80,52 +66,6 @@ struct drm_nouveau_gpuobj_free { uint32_t handle; }; -/* This is needed to avoid a race condition. - * Otherwise you may be writing in the fetch area. - * Is this large enough, as it's only 32 bytes, and the maximum fetch size is 256 bytes? - */ -#define NOUVEAU_DMA_SKIPS 8 - -#define NOUVEAU_MEM_FB 0x00000001 -#define NOUVEAU_MEM_AGP 0x00000002 -#define NOUVEAU_MEM_FB_ACCEPTABLE 0x00000004 -#define NOUVEAU_MEM_AGP_ACCEPTABLE 0x00000008 -#define NOUVEAU_MEM_PCI 0x00000010 -#define NOUVEAU_MEM_PCI_ACCEPTABLE 0x00000020 -#define NOUVEAU_MEM_PINNED 0x00000040 -#define NOUVEAU_MEM_USER_BACKED 0x00000080 -#define NOUVEAU_MEM_MAPPED 0x00000100 -#define NOUVEAU_MEM_TILE 0x00000200 -#define NOUVEAU_MEM_TILE_ZETA 0x00000400 -#define NOUVEAU_MEM_INSTANCE 0x01000000 /* internal */ -#define NOUVEAU_MEM_NOTIFIER 0x02000000 /* internal */ -#define NOUVEAU_MEM_NOVM 0x04000000 /* internal */ -#define NOUVEAU_MEM_USER 0x08000000 /* internal */ -#define NOUVEAU_MEM_INTERNAL (NOUVEAU_MEM_INSTANCE | \ - NOUVEAU_MEM_NOTIFIER | \ - NOUVEAU_MEM_NOVM | \ - NOUVEAU_MEM_USER) - -struct drm_nouveau_mem_alloc { - int flags; - int alignment; - uint64_t size; // in bytes - uint64_t offset; - drm_handle_t map_handle; -}; - -struct drm_nouveau_mem_free { - uint64_t offset; - int flags; -}; - -struct drm_nouveau_mem_tile { - uint64_t offset; - uint64_t delta; - uint64_t size; - int flags; -}; - /* FIXME : maybe unify {GET,SET}PARAMs */ #define NOUVEAU_GETPARAM_PCI_VENDOR 3 #define NOUVEAU_GETPARAM_PCI_DEVICE 4 @@ -136,15 +76,12 @@ struct drm_nouveau_mem_tile { #define NOUVEAU_GETPARAM_AGP_SIZE 9 #define NOUVEAU_GETPARAM_PCI_PHYSICAL 10 #define NOUVEAU_GETPARAM_CHIPSET_ID 11 -#define NOUVEAU_GETPARAM_MM_ENABLED 12 -#define NOUVEAU_GETPARAM_VM_VRAM_BASE 13 +#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12 struct drm_nouveau_getparam { uint64_t param; uint64_t value; }; -#define NOUVEAU_SETPARAM_CMDBUF_LOCATION 1 -#define NOUVEAU_SETPARAM_CMDBUF_SIZE 2 struct drm_nouveau_setparam { uint64_t param; uint64_t value; @@ -228,8 +165,12 @@ struct drm_nouveau_gem_unpin { uint32_t handle; }; +#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 +#define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002 +#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 struct drm_nouveau_gem_cpu_prep { uint32_t handle; + uint32_t flags; }; struct drm_nouveau_gem_cpu_fini { @@ -238,38 +179,19 @@ struct drm_nouveau_gem_cpu_fini { struct drm_nouveau_gem_tile { uint32_t handle; - uint32_t delta; + uint32_t offset; uint32_t size; - uint32_t flags; -}; - -enum nouveau_card_type { - NV_UNKNOWN =0, - NV_04 =4, - NV_05 =5, - NV_10 =10, - NV_11 =11, - NV_17 =17, - NV_20 =20, - NV_30 =30, - NV_40 =40, - NV_44 =44, - NV_50 =50, - NV_LAST =0xffff, + uint32_t tile_mode; + uint32_t tile_flags; }; enum nouveau_bus_type { - NV_AGP =0, - NV_PCI =1, - NV_PCIE =2, + NV_AGP = 0, + NV_PCI = 1, + NV_PCIE = 2, }; -#define NOUVEAU_MAX_SAREA_CLIPRECTS 16 - struct drm_nouveau_sarea { - /* the cliprects */ - struct drm_clip_rect boxes[NOUVEAU_MAX_SAREA_CLIPRECTS]; - unsigned int nbox; }; #define DRM_NOUVEAU_CARD_INIT 0x00 @@ -280,19 +202,13 @@ struct drm_nouveau_sarea { #define DRM_NOUVEAU_GROBJ_ALLOC 0x05 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x06 #define DRM_NOUVEAU_GPUOBJ_FREE 0x07 -#define DRM_NOUVEAU_MEM_ALLOC 0x08 -#define DRM_NOUVEAU_MEM_FREE 0x09 -#define DRM_NOUVEAU_MEM_TILE 0x0a -#define DRM_NOUVEAU_SUSPEND 0x0b -#define DRM_NOUVEAU_RESUME 0x0c #define DRM_NOUVEAU_GEM_NEW 0x40 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41 #define DRM_NOUVEAU_GEM_PUSHBUF_CALL 0x42 -#define DRM_NOUVEAU_GEM_PIN 0x43 -#define DRM_NOUVEAU_GEM_UNPIN 0x44 +#define DRM_NOUVEAU_GEM_PIN 0x43 /* !KMS only */ +#define DRM_NOUVEAU_GEM_UNPIN 0x44 /* !KMS only */ #define DRM_NOUVEAU_GEM_CPU_PREP 0x45 #define DRM_NOUVEAU_GEM_CPU_FINI 0x46 -#define DRM_NOUVEAU_GEM_TILE 0x47 -#define DRM_NOUVEAU_GEM_INFO 0x48 +#define DRM_NOUVEAU_GEM_INFO 0x47 #endif /* __NOUVEAU_DRM_H__ */ |