diff options
Diffstat (limited to 'shared-core/radeon_ms_reg.h')
| -rw-r--r-- | shared-core/radeon_ms_reg.h | 1787 |
1 files changed, 0 insertions, 1787 deletions
diff --git a/shared-core/radeon_ms_reg.h b/shared-core/radeon_ms_reg.h deleted file mode 100644 index 25063990..00000000 --- a/shared-core/radeon_ms_reg.h +++ /dev/null @@ -1,1787 +0,0 @@ -/* - * Copyright 2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef __RADEON_REG_H__ -#define __RADEON_REG_H__ - -#define MC_FB_LOCATION 0x00000148 -#define MC_FB_LOCATION__MC_FB_START__MASK 0x0000FFFF -#define MC_FB_LOCATION__MC_FB_START__SHIFT 0 -#define MC_FB_LOCATION__MC_FB_TOP__MASK 0xFFFF0000 -#define MC_FB_LOCATION__MC_FB_TOP__SHIFT 16 -#define MC_AGP_LOCATION 0x0000014C -#define MC_AGP_LOCATION__MC_AGP_START__MASK 0x0000FFFF -#define MC_AGP_LOCATION__MC_AGP_START__SHIFT 0 -#define MC_AGP_LOCATION__MC_AGP_TOP__MASK 0xFFFF0000 -#define MC_AGP_LOCATION__MC_AGP_TOP__SHIFT 16 -#define AGP_COMMAND 0x00000F60 -#define AGP_COMMAND__DATA_RATE__MASK 0x00000007 -#define AGP_COMMAND__DATA_RATE__SHIFT 0 -#define DATA_RATE__v2_1X 0x1 -#define DATA_RATE__v2_2X 0x2 -#define DATA_RATE__v2_4X 0x4 -#define DATA_RATE__v3_4X 0x1 -#define DATA_RATE__v3_8X 0x2 -#define AGP_COMMAND__AGP_EN 0x00000100 -#define AGP_COMMAND__SBA_EN 0x00000200 -#define AGP_COMMAND__RQ_DEPTH__MASK 0xFF000000 -#define AGP_COMMAND__RQ_DEPTH__SHIFT 24 -#define AGP_COMMAND__FW_EN 0x00000010 -#define AGP_COMMAND__MODE_4G_EN 0x00000020 -#define AGP_COMMAND__PARQSZ__MASK 0x0000E000 -#define AGP_COMMAND__PARQSZ__SHIFT 13 -#define AGP_STATUS 0x00000F5C -#define AGP_STATUS__RATE1X 0x00000001 -#define AGP_STATUS__RATE2X 0x00000002 -#define AGP_STATUS__RATE4X 0x00000004 -#define AGP_STATUS__SBA 0x00000200 -#define AGP_STATUS__RQ__MASK 0xFF000000 -#define AGP_STATUS__RQ__SHIFT 24 -#define AGP_STATUS__FW 0x00000010 -#define AGP_STATUS__MODE_4G 0x00000020 -#define AGP_STATUS__RATE1X_4X 0x00000001 -#define AGP_STATUS__RATE2X_8X 0x00000002 -#define AGP_STATUS__MODE_AGP30 0x00000008 -#define AGP_STATUS__CAL_CYCLE__MASK 0x00001C00 -#define AGP_STATUS__CAL_CYCLE__SHIFT 10 -#define AGP_STATUS__ISOCH_SUPPORT 0x00020000 -#define AGP_BASE 0x00000170 -#define AGP_BASE__AGP_BASE_ADDR__MASK 0xFFFFFFFF -#define AGP_BASE__AGP_BASE_ADDR__SHIFT 0 -#define AGP_BASE_2 0x0000015C -#define AGP_BASE_2__AGP_BASE_ADDR_2__MASK 0x0000000F -#define AGP_BASE_2__AGP_BASE_ADDR_2__SHIFT 0 -#define CONFIG_MEMSIZE 0x000000F8 -#define CONFIG_MEMSIZE__CONFIG_MEMSIZE__MASK 0x1F000000 -#define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 24 -#define CONFIG_MEMSIZE__CONFIG_MEMSIZE_R2__MASK 0x1FF00000 -#define CONFIG_MEMSIZE__CONFIG_MEMSIZE_R2__SHIFT 20 -#define CONFIG_APER_0_BASE 0x00000100 -#define CONFIG_APER_0_BASE__APER_0_BASE__MASK 0xFE000000 -#define CONFIG_APER_0_BASE__APER_0_BASE__SHIFT 25 -#define CONFIG_APER_1_BASE 0x00000104 -#define CONFIG_APER_1_BASE__APER_1_BASE__MASK 0xFF000000 -#define CONFIG_APER_1_BASE__APER_1_BASE__SHIFT 24 -#define CONFIG_APER_SIZE 0x00000108 -#define CONFIG_APER_SIZE__APER_SIZE__MASK 0x0F000000 -#define CONFIG_APER_SIZE__APER_SIZE__SHIFT 24 -#define GEN_INT_CNTL 0x00000040 -#define GEN_INT_CNTL__CRTC_VBLANK 0x00000001 -#define GEN_INT_CNTL__CRTC_VLINE 0x00000002 -#define GEN_INT_CNTL__CRTC_VSYNC 0x00000004 -#define GEN_INT_CNTL__SNAPSHOT 0x00000008 -#define GEN_INT_CNTL__FP_DETECT 0x00000010 -#define GEN_INT_CNTL__CRTC2_VLINE 0x00000020 -#define GEN_INT_CNTL__DMA_VIPH0_INT_EN 0x00001000 -#define GEN_INT_CNTL__CRTC2_VSYNC 0x00000040 -#define GEN_INT_CNTL__SNAPSHOT2 0x00000080 -#define GEN_INT_CNTL__CRTC2_VBLANK 0x00000200 -#define GEN_INT_CNTL__FP2_DETECT 0x00000400 -#define GEN_INT_CNTL__VSYNC_DIFF_OVER_LIMIT 0x00000800 -#define GEN_INT_CNTL__DMA_VIPH1_INT_EN 0x00002000 -#define GEN_INT_CNTL__DMA_VIPH2_INT_EN 0x00004000 -#define GEN_INT_CNTL__DMA_VIPH3_INT_EN 0x00008000 -#define GEN_INT_CNTL__I2C_INT_EN 0x00020000 -#define GEN_INT_CNTL__GUI_IDLE 0x00080000 -#define GEN_INT_CNTL__VIPH_INT_EN 0x01000000 -#define GEN_INT_CNTL__SW_INT_EN 0x02000000 -#define GEN_INT_CNTL__GEYSERVILLE 0x08000000 -#define GEN_INT_CNTL__DVI_I2C_INT 0x20000000 -#define GEN_INT_CNTL__GUIDMA 0x40000000 -#define GEN_INT_CNTL__VIDDMA 0x80000000 -#define GEN_INT_CNTL__TIMER_INT 0x00010000 -#define GEN_INT_CNTL__IDCT_INT_EN 0x08000000 -#define GEN_INT_STATUS 0x00000044 -#define GEN_INT_STATUS__CRTC_VBLANK_STAT 0x00000001 -#define GEN_INT_STATUS__CRTC_VBLANK_STAT_AK 0x00000001 -#define GEN_INT_STATUS__CRTC_VLINE_STAT 0x00000002 -#define GEN_INT_STATUS__CRTC_VLINE_STAT_AK 0x00000002 -#define GEN_INT_STATUS__CRTC_VSYNC_STAT 0x00000004 -#define GEN_INT_STATUS__CRTC_VSYNC_STAT_AK 0x00000004 -#define GEN_INT_STATUS__SNAPSHOT_STAT 0x00000008 -#define GEN_INT_STATUS__SNAPSHOT_STAT_AK 0x00000008 -#define GEN_INT_STATUS__FP_DETECT_STAT 0x00000010 -#define GEN_INT_STATUS__FP_DETECT_STAT_AK 0x00000010 -#define GEN_INT_STATUS__CRTC2_VLINE_STAT 0x00000020 -#define GEN_INT_STATUS__CRTC2_VLINE_STAT_AK 0x00000020 -#define GEN_INT_STATUS__CRTC2_VSYNC_STAT 0x00000040 -#define GEN_INT_STATUS__CRTC2_VSYNC_STAT_AK 0x00000040 -#define GEN_INT_STATUS__SNAPSHOT2_STAT 0x00000080 -#define GEN_INT_STATUS__SNAPSHOT2_STAT_AK 0x00000080 -#define GEN_INT_STATUS__CAP0_INT_ACTIVE 0x00000100 -#define GEN_INT_STATUS__CRTC2_VBLANK_STAT 0x00000200 -#define GEN_INT_STATUS__CRTC2_VBLANK_STAT_AK 0x00000200 -#define GEN_INT_STATUS__FP2_DETECT_STAT 0x00000400 -#define GEN_INT_STATUS__FP2_DETECT_STAT_AK 0x00000400 -#define GEN_INT_STATUS__VSYNC_DIFF_OVER_LIMIT_STAT 0x00000800 -#define GEN_INT_STATUS__VSYNC_DIFF_OVER_LIMIT_STAT_AK 0x00000800 -#define GEN_INT_STATUS__DMA_VIPH0_INT 0x00001000 -#define GEN_INT_STATUS__DMA_VIPH0_INT_AK 0x00001000 -#define GEN_INT_STATUS__DMA_VIPH1_INT 0x00002000 -#define GEN_INT_STATUS__DMA_VIPH1_INT_AK 0x00002000 -#define GEN_INT_STATUS__DMA_VIPH2_INT 0x00004000 -#define GEN_INT_STATUS__DMA_VIPH2_INT_AK 0x00004000 -#define GEN_INT_STATUS__DMA_VIPH3_INT 0x00008000 -#define GEN_INT_STATUS__DMA_VIPH3_INT_AK 0x00008000 -#define GEN_INT_STATUS__I2C_INT 0x00020000 -#define GEN_INT_STATUS__I2C_INT_AK 0x00020000 -#define GEN_INT_STATUS__GUI_IDLE_STAT 0x00080000 -#define GEN_INT_STATUS__GUI_IDLE_STAT_AK 0x00080000 -#define GEN_INT_STATUS__VIPH_INT 0x01000000 -#define GEN_INT_STATUS__SW_INT 0x02000000 -#define GEN_INT_STATUS__SW_INT_AK 0x02000000 -#define GEN_INT_STATUS__SW_INT_SET 0x04000000 -#define GEN_INT_STATUS__GEYSERVILLE_STAT 0x08000000 -#define GEN_INT_STATUS__GEYSERVILLE_STAT_AK 0x08000000 -#define GEN_INT_STATUS__DVI_I2C_INT_STAT 0x20000000 -#define GEN_INT_STATUS__DVI_I2C_INT_AK 0x20000000 -#define GEN_INT_STATUS__GUIDMA_STAT 0x40000000 -#define GEN_INT_STATUS__GUIDMA_AK 0x40000000 -#define GEN_INT_STATUS__VIDDMA_STAT 0x80000000 -#define GEN_INT_STATUS__VIDDMA_AK 0x80000000 -#define GEN_INT_STATUS__TIMER_INT_STAT 0x00010000 -#define GEN_INT_STATUS__TIMER_INT_STAT_AK 0x00010000 -#define GEN_INT_STATUS__IDCT_INT_STAT 0x08000000 -#define GEN_INT_STATUS__IDCT_INT_STAT_AK 0x08000000 -#define RB2D_DSTCACHE_MODE 0x00003428 -#define RB2D_DSTCACHE_MODE__DC_BYPASS__MASK 0x00000003 -#define RB2D_DSTCACHE_MODE__DC_BYPASS__SHIFT 0 -#define RB2D_DSTCACHE_MODE__DC_LINE_SIZE__MASK 0x0000000C -#define RB2D_DSTCACHE_MODE__DC_LINE_SIZE__SHIFT 2 -#define RB2D_DSTCACHE_MODE__DC_AUTOFLUSH_ENABLE__MASK 0x00000300 -#define RB2D_DSTCACHE_MODE__DC_AUTOFLUSH_ENABLE__SHIFT 8 -#define RB2D_DSTCACHE_MODE__DC_FORCE_RMW 0x00010000 -#define RB2D_DSTCACHE_MODE__DC_DISABLE_RI_FILL 0x01000000 -#define RB2D_DSTCACHE_MODE__DC_DISABLE_RI_READ 0x02000000 -#define RB2D_DSTCACHE_MODE__DC_AUTOFREE_ENABLE__MASK 0x00000C00 -#define RB2D_DSTCACHE_MODE__DC_AUTOFREE_ENABLE__SHIFT 10 -#define RB2D_DSTCACHE_MODE__DC_DISABLE 0x04000000 -#define RB2D_DSTCACHE_MODE__DC_DISABLE_IGNORE_PE 0x00020000 -#define RB2D_DSTCACHE_CTLSTAT 0x0000342C -#define RB2D_DSTCACHE_CTLSTAT__DC_FLUSH__MASK 0x00000003 -#define RB2D_DSTCACHE_CTLSTAT__DC_FLUSH__SHIFT 0 -#define RB2D_DSTCACHE_CTLSTAT__DC_FREE__MASK 0x0000000C -#define RB2D_DSTCACHE_CTLSTAT__DC_FREE__SHIFT 2 -#define RB2D_DSTCACHE_CTLSTAT__DC_BUSY 0x80000000 -#define RB3D_DSTCACHE_CTLSTAT 0x0000325C -#define RB3D_DSTCACHE_CTLSTAT__DC_FLUSH__MASK 0x00000003 -#define RB3D_DSTCACHE_CTLSTAT__DC_FLUSH__SHIFT 0 -#define RB3D_DSTCACHE_CTLSTAT__DC_FREE__MASK 0x0000000C -#define RB3D_DSTCACHE_CTLSTAT__DC_FREE__SHIFT 2 -#define RB3D_DSTCACHE_CTLSTAT__DC_BUSY 0x80000000 -#define RB3D_DSTCACHE_CTLSTAT_R3 0x00004E4C -#define RB3D_DSTCACHE_CTLSTAT_R3__DC_FLUSH__MASK 0x00000003 -#define RB3D_DSTCACHE_CTLSTAT_R3__DC_FLUSH__SHIFT 0 -#define RB3D_DSTCACHE_CTLSTAT_R3__DC_FREE__MASK 0x0000000C -#define RB3D_DSTCACHE_CTLSTAT_R3__DC_FREE__SHIFT 2 -#define RB3D_DSTCACHE_CTLSTAT_R3__DC_FINISH 0x00000010 -#define RB3D_ZCACHE_CTLSTAT 0x00003254 -#define RB3D_ZCACHE_CTLSTAT__ZC_FLUSH 0x00000001 -#define RB3D_ZCACHE_CTLSTAT__ZC_FREE 0x00000004 -#define RB3D_ZCACHE_CTLSTAT__ZC_DIRTY 0x40000000 -#define RB3D_ZCACHE_CTLSTAT__ZC_BUSY 0x80000000 -#define RB3D_ZCACHE_CTLSTAT_R3 0x00004F18 -#define RB3D_ZCACHE_CTLSTAT_R3__ZC_FLUSH 0x00000001 -#define RB3D_ZCACHE_CTLSTAT_R3__ZC_FREE 0x00000002 -#define RB3D_ZCACHE_CTLSTAT_R3__ZC_BUSY 0x80000000 -#define SCRATCH_REG0 0x000015E0 -#define SCRATCH_REG0__SCRATCH_REG0__MASK 0xFFFFFFFF -#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0 -#define SCRATCH_REG1 0x000015E4 -#define SCRATCH_REG1__SCRATCH_REG1__MASK 0xFFFFFFFF -#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0 -#define SCRATCH_REG2 0x000015E8 -#define SCRATCH_REG2__SCRATCH_REG2__MASK 0xFFFFFFFF -#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0 -#define SCRATCH_REG3 0x000015EC -#define SCRATCH_REG3__SCRATCH_REG3__MASK 0xFFFFFFFF -#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0 -#define SCRATCH_REG4 0x000015F0 -#define SCRATCH_REG4__SCRATCH_REG4__MASK 0xFFFFFFFF -#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0 -#define SCRATCH_REG5 0x000015F4 -#define SCRATCH_REG5__SCRATCH_REG5__MASK 0xFFFFFFFF -#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0 -#define SCRATCH_REG6 0x000015F8 -#define SCRATCH_REG6__SCRATCH_REG6__MASK 0xFFFFFFFF -#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0 -#define SCRATCH_REG7 0x000015FC -#define SCRATCH_REG7__SCRATCH_REG7__MASK 0xFFFFFFFF -#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0 -#define SC_SCISSOR0 0x000043E0 -#define SC_SCISSOR0__XS0__MASK 0x00001FFF -#define SC_SCISSOR0__XS0__SHIFT 0 -#define SC_SCISSOR0__YS0__MASK 0x03FFE000 -#define SC_SCISSOR0__YS0__SHIFT 13 -#define SC_SCISSOR1 0x000043E4 -#define SC_SCISSOR1__XS1__MASK 0x00001FFF -#define SC_SCISSOR1__XS1__SHIFT 0 -#define SC_SCISSOR1__YS1__MASK 0x03FFE000 -#define SC_SCISSOR1__YS1__SHIFT 13 -#define PCIE_INDEX 0x00000030 -#define PCIE_INDEX__PCIE_INDEX__MASK 0x000007FF -#define PCIE_INDEX__PCIE_INDEX__SHIFT 0 -#define PCIE_DATA 0x00000034 -#define PCIE_DATA__PCIE_DATA__MASK 0xFFFFFFFF -#define PCIE_DATA__PCIE_DATA__SHIFT 0 -#define PCIE_TX_GART_CNTL 0x00000010 -#define PCIE_TX_GART_CNTL__GART_EN 0x00000001 -#define PCIE_TX_GART_CNTL__GART_UNMAPPED_ACCESS__MASK 0x00000006 -#define PCIE_TX_GART_CNTL__GART_UNMAPPED_ACCESS__SHIFT 1 -#define GART_UNMAPPED_ACCESS__PTHRU 0x0 -#define GART_UNMAPPED_ACCESS__CLAMP 0x1 -#define GART_UNMAPPED_ACCESS__DISCARD 0x3 -#define PCIE_TX_GART_CNTL__GART_MODE__MASK 0x00000018 -#define PCIE_TX_GART_CNTL__GART_MODE__SHIFT 3 -#define GART_MODE__CACHE_32x128 0x0 -#define GART_MODE__CACHE_8x4x128 0x1 -#define PCIE_TX_GART_CNTL__GART_CHK_RW_VALID_EN 0x00000020 -#define PCIE_TX_GART_CNTL__GART_RDREQPATH_SEL__MASK 0x00000040 -#define PCIE_TX_GART_CNTL__GART_RDREQPATH_SEL__SHIFT 6 -#define GART_RDREQPATH_SEL__HDP 0x0 -#define GART_RDREQPATH_SEL__DRQMC 0x1 -#define PCIE_TX_GART_CNTL__GART_INVALIDATE_TLB 0x00000100 -#define PCIE_TX_GART_DISCARD_RD_ADDR_LO 0x00000011 -#define PCIE_TX_GART_DISCARD_RD_ADDR_LO__GART_DISCARD_RD_ADDR_LO__MASK 0xFFFFFFFF -#define PCIE_TX_GART_DISCARD_RD_ADDR_LO__GART_DISCARD_RD_ADDR_LO__SHIFT 0 -#define PCIE_TX_GART_DISCARD_RD_ADDR_HI 0x00000012 -#define PCIE_TX_GART_DISCARD_RD_ADDR_HI__GART_DISCARD_RD_ADDR_HI__MASK 0x000000FF -#define PCIE_TX_GART_DISCARD_RD_ADDR_HI__GART_DISCARD_RD_ADDR_HI__SHIFT 0 -#define PCIE_TX_GART_BASE 0x00000013 -#define PCIE_TX_GART_BASE__GART_BASE__MASK 0xFFFFFFFF -#define PCIE_TX_GART_BASE__GART_BASE__SHIFT 0 -#define PCIE_TX_GART_START_LO 0x00000014 -#define PCIE_TX_GART_START_LO__GART_START_LO__MASK 0xFFFFFFFF -#define PCIE_TX_GART_START_LO__GART_START_LO__SHIFT 0 -#define PCIE_TX_GART_START_HI 0x00000015 -#define PCIE_TX_GART_START_HI__GART_START_HI__MASK 0x000000FF -#define PCIE_TX_GART_START_HI__GART_START_HI__SHIFT 0 -#define PCIE_TX_GART_END_LO 0x00000016 -#define PCIE_TX_GART_END_LO__GART_END_LO__MASK 0xFFFFFFFF -#define PCIE_TX_GART_END_LO__GART_END_LO__SHIFT 0 -#define PCIE_TX_GART_END_HI 0x00000017 -#define PCIE_TX_GART_END_HI__GART_END_HI__MASK 0x000000FF -#define PCIE_TX_GART_END_HI__GART_END_HI__SHIFT 0 -#define PCIE_TX_GART_ERROR 0x00000018 -#define PCIE_TX_GART_ERROR__GART_UNMAPPED 0x00000002 -#define PCIE_TX_GART_ERROR__GART_INVALID_READ 0x00000004 -#define PCIE_TX_GART_ERROR__GART_INVALID_WRITE 0x00000008 -#define PCIE_TX_GART_ERROR__GART_INVALID_ADDR__MASK 0xFFFFFFF0 -#define PCIE_TX_GART_ERROR__GART_INVALID_ADDR__SHIFT 4 -#define CP_CSQ_MODE 0x00000744 -#define CP_CSQ_MODE__INDIRECT2_START__MASK 0x0000007F -#define CP_CSQ_MODE__INDIRECT2_START__SHIFT 0 -#define CP_CSQ_MODE__INDIRECT1_START__MASK 0x00007F00 -#define CP_CSQ_MODE__INDIRECT1_START__SHIFT 8 -#define CP_CSQ_MODE__CSQ_INDIRECT2_MODE 0x04000000 -#define CP_CSQ_MODE__CSQ_INDIRECT2_ENABLE 0x08000000 -#define CP_CSQ_MODE__CSQ_INDIRECT1_MODE 0x10000000 -#define CP_CSQ_MODE__CSQ_INDIRECT1_ENABLE 0x20000000 -#define CP_CSQ_MODE__CSQ_PRIMARY_MODE 0x40000000 -#define CP_CSQ_MODE__CSQ_PRIMARY_ENABLE 0x80000000 -#define CP_RB_CNTL 0x00000704 -#define CP_RB_CNTL__RB_BUFSZ__MASK 0x0000003F -#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0 -#define CP_RB_CNTL__RB_BLKSZ__MASK 0x00003F00 -#define CP_RB_CNTL__RB_BLKSZ__SHIFT 8 -#define CP_RB_CNTL__BUF_SWAP__MASK 0x00030000 -#define CP_RB_CNTL__BUF_SWAP__SHIFT 16 -#define CP_RB_CNTL__MAX_FETCH__MASK 0x000C0000 -#define CP_RB_CNTL__MAX_FETCH__SHIFT 18 -#define CP_RB_CNTL__RB_NO_UPDATE 0x08000000 -#define CP_RB_CNTL__RB_RPTR_WR_ENA 0x80000000 -#define CP_RB_BASE 0x00000700 -#define CP_RB_BASE__RB_BASE__MASK 0xFFFFFFFC -#define CP_RB_BASE__RB_BASE__SHIFT 2 -#define CP_RB_RPTR_ADDR 0x0000070C -#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__MASK 0x00000003 -#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0 -#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__MASK 0xFFFFFFFC -#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 2 -#define CP_RB_RPTR 0x00000710 -#define CP_RB_RPTR__RB_RPTR__MASK 0x007FFFFF -#define CP_RB_RPTR__RB_RPTR__SHIFT 0 -#define CP_RB_RPTR_WR 0x0000071C -#define CP_RB_RPTR_WR__RB_RPTR_WR__MASK 0x007FFFFF -#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0 -#define CP_RB_WPTR 0x00000714 -#define CP_RB_WPTR__RB_WPTR__MASK 0x007FFFFF -#define CP_RB_WPTR__RB_WPTR__SHIFT 0 -#define CP_RB_WPTR_DELAY 0x00000718 -#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__MASK 0x0FFFFFFF -#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0 -#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__MASK 0xF0000000 -#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 28 -#define SCRATCH_UMSK 0x00000770 -#define SCRATCH_UMSK__SCRATCH_UMSK__MASK 0x0000003F -#define SCRATCH_UMSK__SCRATCH_UMSK__SHIFT 0 -#define SCRATCH_UMSK__SCRATCH_SWAP__MASK 0x00030000 -#define SCRATCH_UMSK__SCRATCH_SWAP__SHIFT 16 -#define SCRATCH_UMSK__SCRATCH_UMSK_R2__MASK 0x000000FF -#define SCRATCH_UMSK__SCRATCH_UMSK_R2__SHIFT 0 -#define SCRATCH_ADDR 0x00000774 -#define SCRATCH_ADDR__SCRATCH_ADDR__MASK 0xFFFFFFE0 -#define SCRATCH_ADDR__SCRATCH_ADDR__SHIFT 5 -#define CP_ME_RAM_ADDR 0x000007D4 -#define CP_ME_RAM_ADDR__ME_RAM_ADDR__MASK 0x000000FF -#define CP_ME_RAM_ADDR__ME_RAM_ADDR__SHIFT 0 -#define CP_ME_RAM_DATAH 0x000007DC -#define CP_ME_RAM_DATAH__ME_RAM_DATAH__MASK 0x0000003F -#define CP_ME_RAM_DATAH__ME_RAM_DATAH__SHIFT 0 -#define CP_ME_RAM_DATAH__ME_RAM_DATAH_R3__MASK 0x000000FF -#define CP_ME_RAM_DATAH__ME_RAM_DATAH_R3__SHIFT 0 -#define CP_ME_RAM_DATAL 0x000007E0 -#define CP_ME_RAM_DATAL__ME_RAM_DATAL__MASK 0xFFFFFFFF -#define CP_ME_RAM_DATAL__ME_RAM_DATAL__SHIFT 0 -#define CP_CSQ_CNTL 0x00000740 -#define CP_CSQ_CNTL__CSQ_CNT_PRIMARY__MASK 0x000000FF -#define CP_CSQ_CNTL__CSQ_CNT_PRIMARY__SHIFT 0 -#define CP_CSQ_CNTL__CSQ_CNT_INDIRECT__MASK 0x0000FF00 -#define CP_CSQ_CNTL__CSQ_CNT_INDIRECT__SHIFT 8 -#define CP_CSQ_CNTL__CSQ_MODE__MASK 0xF0000000 -#define CP_CSQ_CNTL__CSQ_MODE__SHIFT 28 -#define CSQ_MODE__CSQ_PRIDIS_INDDIS 0x0 -#define CSQ_MODE__CSQ_PRIPIO_INDDIS 0x1 -#define CSQ_MODE__CSQ_PRIBM_INDDIS 0x2 -#define CSQ_MODE__CSQ_PRIPIO_INDBM 0x3 -#define CSQ_MODE__CSQ_PRIBM_INDBM 0x4 -#define CSQ_MODE__CSQ_PRIPIO_INDPIO 0xF -#define CP_CSQ_CNTL__CSQ_CNT_PRIMARY_R2__MASK 0x000001FF -#define CP_CSQ_CNTL__CSQ_CNT_PRIMARY_R2__SHIFT 0 -#define CP_CSQ_CNTL__CSQ_CNT_INDIRECT_R2__MASK 0x0003FE00 -#define CP_CSQ_CNTL__CSQ_CNT_INDIRECT_R2__SHIFT 9 -#define CP_CSQ_CNTL__CSQ_CNT_INDIRECT2__MASK 0x07FC0000 -#define CP_CSQ_CNTL__CSQ_CNT_INDIRECT2__SHIFT 18 -#define CRTC_GEN_CNTL 0x00000050 -#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001 -#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002 -#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010 -#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH__MASK 0x00000F00 -#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH__SHIFT 8 -#define CRTC_PIX_WIDTH__4BPP 0x100 -#define CRTC_PIX_WIDTH__8BPP 0x200 -#define CRTC_PIX_WIDTH__15BPP 0x300 -#define CRTC_PIX_WIDTH__16BPP 0x400 -#define CRTC_PIX_WIDTH__24BPP 0x500 -#define CRTC_PIX_WIDTH__34BPP 0x600 -#define CRTC_PIX_WIDTH__16BPP_4444 0x700 -#define CRTC_PIX_WIDTH__16BPP_88 0x800 -#define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000 -#define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000 -#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE__MASK 0x00060000 -#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE__SHIFT 17 -#define CRTC_GEN_CNTL__CRTC_CUR_MODE__MASK 0x00700000 -#define CRTC_GEN_CNTL__CRTC_CUR_MODE__SHIFT 20 -#define CRTC_CUR_MODE__PREMULTI_ALPHA 0x2 -#define CRTC_CUR_MODE__COLOR24BPP 0x1 -#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000 -#define CRTC_GEN_CNTL__CRTC_EN 0x02000000 -#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000 -#define CRTC_GEN_CNTL__CRTC_MODE9_COLOR_ORDER 0x00001000 -#define CRTC_EXT_CNTL 0x00000054 -#define CRTC_EXT_CNTL__CRTC_VGA_XOVERSCAN 0x00000001 -#define CRTC_EXT_CNTL__VGA_BLINK_RATE__MASK 0x00000006 -#define CRTC_EXT_CNTL__VGA_BLINK_RATE__SHIFT 1 -#define CRTC_EXT_CNTL__VGA_ATI_LINEAR 0x00000008 -#define CRTC_EXT_CNTL__VGA_128KAP_PAGING 0x00000010 -#define CRTC_EXT_CNTL__VGA_TEXT_132 0x00000020 -#define CRTC_EXT_CNTL__VGA_XCRT_CNT_EN 0x00000040 -#define CRTC_EXT_CNTL__CRTC_HSYNC_DIS 0x00000100 -#define CRTC_EXT_CNTL__CRTC_VSYNC_DIS 0x00000200 -#define CRTC_EXT_CNTL__CRTC_DISPLAY_DIS 0x00000400 -#define CRTC_EXT_CNTL__CRTC_SYNC_TRISTATE 0x00000800 -#define CRTC_EXT_CNTL__CRTC_HSYNC_TRISTATE 0x00001000 -#define CRTC_EXT_CNTL__CRTC_VSYNC_TRISTATE 0x00002000 -#define CRTC_EXT_CNTL__CRT_ON 0x00008000 -#define CRTC_EXT_CNTL__VGA_CUR_B_TEST 0x00020000 -#define CRTC_EXT_CNTL__VGA_PACK_DIS 0x00040000 -#define CRTC_EXT_CNTL__VGA_MEM_PS_EN 0x00080000 -#define CRTC_EXT_CNTL__VCRTC_IDX_MASTER__MASK 0x7F000000 -#define CRTC_EXT_CNTL__VCRTC_IDX_MASTER__SHIFT 24 -#define CRTC_H_TOTAL_DISP 0x00000200 -#define CRTC_H_TOTAL_DISP__CRTC_H_TOTAL__MASK 0x000003FF -#define CRTC_H_TOTAL_DISP__CRTC_H_TOTAL__SHIFT 0 -#define CRTC_H_TOTAL_DISP__CRTC_H_DISP__MASK 0x01FF0000 -#define CRTC_H_TOTAL_DISP__CRTC_H_DISP__SHIFT 16 -#define CRTC_H_SYNC_STRT_WID 0x00000204 -#define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_STRT_PIX__MASK 0x00000007 -#define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_STRT_PIX__SHIFT 0 -#define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_STRT_CHAR__MASK 0x00001FF8 -#define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_STRT_CHAR__SHIFT 3 -#define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_WID__MASK 0x003F0000 -#define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_WID__SHIFT 16 -#define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_POL 0x00800000 -#define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_SKEW_TUNE__MASK 0x07000000 -#define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_SKEW_TUNE__SHIFT 24 -#define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_SKEW_TUNE_MODE 0x10000000 -#define CRTC_V_TOTAL_DISP 0x00000208 -#define CRTC_V_TOTAL_DISP__CRTC_V_TOTAL__MASK 0x00000FFF -#define CRTC_V_TOTAL_DISP__CRTC_V_TOTAL__SHIFT 0 -#define CRTC_V_TOTAL_DISP__CRTC_V_DISP__MASK 0x0FFF0000 -#define CRTC_V_TOTAL_DISP__CRTC_V_DISP__SHIFT 16 -#define CRTC_V_SYNC_STRT_WID 0x0000020C -#define CRTC_V_SYNC_STRT_WID__CRTC_V_SYNC_STRT__MASK 0x00000FFF -#define CRTC_V_SYNC_STRT_WID__CRTC_V_SYNC_STRT__SHIFT 0 -#define CRTC_V_SYNC_STRT_WID__CRTC_V_SYNC_WID__MASK 0x001F0000 -#define CRTC_V_SYNC_STRT_WID__CRTC_V_SYNC_WID__SHIFT 16 -#define CRTC_V_SYNC_STRT_WID__CRTC_V_SYNC_POL 0x00800000 -#define CRTC_OFFSET 0x00000224 -#define CRTC_OFFSET__CRTC_OFFSET__MASK 0x07FFFFFF -#define CRTC_OFFSET__CRTC_OFFSET__SHIFT 0 -#define CRTC_OFFSET__CRTC_GUI_TRIG_OFFSET 0x40000000 -#define CRTC_OFFSET__CRTC_OFFSET_LOCK 0x80000000 -#define CRTC_OFFSET__CRTC_OFFSET_R3__MASK 0x0FFFFFFF -#define CRTC_OFFSET__CRTC_OFFSET_R3__SHIFT 0 -#define CRTC_OFFSET_CNTL 0x00000228 -#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE__MASK 0x0000000F -#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE__SHIFT 0 -#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT__MASK 0x000000F0 -#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT__SHIFT 4 -#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000 -#define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000 -#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000 -#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000 -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN__MASK 0x000C0000 -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN__SHIFT 18 -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000 -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000 -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000 -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000 -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000 -#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000 -#define CRTC_OFFSET_CNTL__CRTC_X_Y_MODE_EN_RIGHT 0x00000040 -#define CRTC_OFFSET_CNTL__CRTC_MICRO_TILE_BUFFER_MODE_RIGHT__MASK 0x00000180 -#define CRTC_OFFSET_CNTL__CRTC_MICRO_TILE_BUFFER_MODE_RIGHT__SHIFT 7 -#define CRTC_OFFSET_CNTL__CRTC_X_Y_MODE_EN 0x00000200 -#define CRTC_OFFSET_CNTL__CRTC_MICRO_TILE_BUFFER_MODE__MASK 0x00000C00 -#define CRTC_OFFSET_CNTL__CRTC_MICRO_TILE_BUFFER_MODE__SHIFT 10 -#define CRTC_MICRO_TILE_BUFFER_MODE__AUTO 0x0 -#define CRTC_MICRO_TILE_BUFFER_MODE__SLINE 0x1 -#define CRTC_MICRO_TILE_BUFFER_MODE__DLINE 0x2 -#define CRTC_MICRO_TILE_BUFFER_MODE__DIS 0x3 -#define CRTC_OFFSET_CNTL__CRTC_MICRO_TILE_EN_RIGHT 0x00001000 -#define CRTC_OFFSET_CNTL__CRTC_MICRO_TILE_EN 0x00002000 -#define CRTC_OFFSET_CNTL__CRTC_MACRO_TILE_EN_RIGHT 0x00004000 -#define CRTC_OFFSET_CNTL__CRTC_MACRO_TILE_EN 0x00008000 -#define CRTC_PITCH 0x0000022C -#define CRTC_PITCH__CRTC_PITCH__MASK 0x000007FF -#define CRTC_PITCH__CRTC_PITCH__SHIFT 0 -#define CRTC_PITCH__CRTC_PITCH_RIGHT__MASK 0x07FF0000 -#define CRTC_PITCH__CRTC_PITCH_RIGHT__SHIFT 16 -#define CRTC_MORE_CNTL 0x0000027C -#define CRTC_MORE_CNTL__CRTC_HORZ_BLANK_MODE_SEL 0x00000001 -#define CRTC_MORE_CNTL__CRTC_VERT_BLANK_MODE_SEL 0x00000002 -#define CRTC_MORE_CNTL__CRTC_AUTO_HORZ_CENTER_EN 0x00000004 -#define CRTC_MORE_CNTL__CRTC_AUTO_VERT_CENTER_EN 0x00000008 -#define CRTC_MORE_CNTL__CRTC_H_CUTOFF_ACTIVE_EN 0x00000010 -#define CRTC_MORE_CNTL__CRTC_V_CUTOFF_ACTIVE_EN 0x00000020 -#define CRTC_MORE_CNTL__FORCE_H_EVEN_PIXEL_COUNT 0x00000040 -#define CRTC_MORE_CNTL__RMX_H_FILT_COEFFICIENT__MASK 0x07000000 -#define CRTC_MORE_CNTL__RMX_H_FILT_COEFFICIENT__SHIFT 24 -#define CRTC_MORE_CNTL__RMX_H_FILTER_EN 0x08000000 -#define CRTC_MORE_CNTL__RMX_V_FILT_COEFFICIENT__MASK 0x70000000 -#define CRTC_MORE_CNTL__RMX_V_FILT_COEFFICIENT__SHIFT 28 -#define CRTC_MORE_CNTL__RMX_V_FILTER_EN 0x80000000 -#define CRTC_MORE_CNTL__DSP_RST_HCOUNT 0x00000100 -#define CRTC_MORE_CNTL__DSP_RST_VCOUNT 0x00000200 -#define CRTC_MORE_CNTL__HCOUNT_RST_POS 0x00000400 -#define CRTC_MORE_CNTL__VCOUNT_RST_POS 0x00000800 -#define CRTC_MORE_CNTL__CRTC_FIX_VSYNC_EDGE_POSITION_EN 0x00001000 -#define CRTC_TILE_X0_Y0 0x00000350 -#define CRTC_TILE_X0_Y0__CRTC_TILE_X0__MASK 0x00000FFF -#define CRTC_TILE_X0_Y0__CRTC_TILE_X0__SHIFT 0 -#define CRTC_TILE_X0_Y0__CRTC_TILE_Y0__MASK 0x0FFF0000 -#define CRTC_TILE_X0_Y0__CRTC_TILE_Y0__SHIFT 16 -#define CRTC_TILE_X0_Y0__CRTC_GUI_TRIG_OFFSET 0x40000000 -#define CRTC_TILE_X0_Y0__CRTC_OFFSET_LOCK 0x80000000 -#define DAC_CNTL 0x00000058 -#define DAC_CNTL__DAC_RANGE_CNTL__MASK 0x00000003 -#define DAC_CNTL__DAC_RANGE_CNTL__SHIFT 0 -#define DAC_RANGE_CNTL__PS2 0x2 -#define DAC_RANGE_CNTL__YPbPr 0x3 -#define DAC_CNTL__DAC_BLANKING 0x00000004 -#define DAC_CNTL__DAC_CMP_EN 0x00000008 -#define DAC_CNTL__DAC_CMP_OUT_R 0x00000010 -#define DAC_CNTL__DAC_CMP_OUT_G 0x00000020 -#define DAC_CNTL__DAC_CMP_OUT_B 0x00000040 -#define DAC_CNTL__DAC_CMP_OUTPUT 0x00000080 -#define DAC_CNTL__DAC_8BIT_EN 0x00000100 -#define DAC_CNTL__DAC_4BPP_PIX_ORDER 0x00000200 -#define DAC_CNTL__DAC_TVO_EN 0x00000400 -#define DAC_CNTL__DAC_VGA_ADR_EN 0x00002000 -#define DAC_CNTL__DAC_EXPAND_MODE 0x00004000 -#define DAC_CNTL__DAC_PDWN 0x00008000 -#define DAC_CNTL__CRT_SENSE 0x00010000 -#define DAC_CNTL__CRT_DETECTION_ON 0x00020000 -#define DAC_CNTL__DAC_CRC_CONT_EN 0x00040000 -#define DAC_CNTL__DAC_CRC_EN 0x00080000 -#define DAC_CNTL__DAC_CRC_FIELD 0x00100000 -#define DAC_CNTL__DAC_LUT_COUNTER_LIMIT__MASK 0x00600000 -#define DAC_CNTL__DAC_LUT_COUNTER_LIMIT__SHIFT 21 -#define DAC_CNTL__DAC_LUT_READ_SEL 0x00800000 -#define DAC_CNTL__DAC__MASK 0xFF000000 -#define DAC_CNTL__DAC__SHIFT 24 -#define DAC_CNTL__DAC_CRC_BLANKb_ONLY 0x00000800 -#define DAC_CNTL2 0x0000007C -#define DAC_CNTL2__DAC_CLK_SEL 0x00000001 -#define DAC_CNTL2__DAC2_CLK_SEL 0x00000002 -#define DAC_CNTL2__PALETTE_ACCESS_CNTL 0x00000020 -#define DAC_CNTL2__DAC2_CMP_EN 0x00000080 -#define DAC_CNTL2__DAC2_CMP_OUT_R 0x00000100 -#define DAC_CNTL2__DAC2_CMP_OUT_G 0x00000200 -#define DAC_CNTL2__DAC2_CMP_OUT_B 0x00000400 -#define DAC_CNTL2__DAC2_CMP_OUTPUT 0x00000800 -#define DAC_CNTL2__DAC2_EXPAND_MODE 0x00004000 -#define DAC_CNTL2__CRT2_SENSE 0x00010000 -#define DAC_CNTL2__CRT2_DETECTION_ON 0x00020000 -#define DAC_CNTL2__DAC_CRC2_CONT_EN 0x00040000 -#define DAC_CNTL2__DAC_CRC2_EN 0x00080000 -#define DAC_CNTL2__DAC_CRC2_FIELD 0x00100000 -#define DAC_CNTL2__DAC2_LUT_COUNTER_LIMIT__MASK 0x00600000 -#define DAC_CNTL2__DAC2_LUT_COUNTER_LIMIT__SHIFT 21 -#define DAC_CNTL2__PALETTE_AUTOFILL_PRIMARY_W 0x00000800 -#define DAC_CNTL2__PALETTE_AUTOFILL_PRIMARY_R 0x00000800 -#define DAC_CNTL2__PALETTE_AUTOFILL_SECONDARY_W 0x00001000 -#define DAC_CNTL2__PALETTE_AUTOFILL_SECONDARY_R 0x00001000 -#define DAC_CNTL2__DAC2_CMP_EN_R3 0x00000040 -#define DAC_CNTL2__DAC2_CMP_OUT_R_R3 0x00000080 -#define DAC_CNTL2__DAC2_CMP_OUT_G_R3 0x00000100 -#define DAC_CNTL2__DAC2_CMP_OUT_B_R3 0x00000200 -#define DAC_CNTL2__DAC2_CMP_OUTPUT_R3 0x00000400 -#define DAC_CNTL2__DAC_CRC2_BLANKb_ONLY 0x00020000 -#define DAC_EXT_CNTL 0x00000280 -#define DAC_EXT_CNTL__DAC2_FORCE_BLANK_OFF_EN 0x00000001 -#define DAC_EXT_CNTL__DAC2_FORCE_DATA_EN 0x00000002 -#define DAC_EXT_CNTL__DAC_FORCE_BLANK_OFF_EN 0x00000010 -#define DAC_EXT_CNTL__DAC_FORCE_DATA_EN 0x00000020 -#define DAC_EXT_CNTL__DAC_FORCE_DATA_SEL__MASK 0x000000C0 -#define DAC_EXT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 6 -#define DAC_EXT_CNTL__DAC_FORCE_DATA__MASK 0x0003FF00 -#define DAC_EXT_CNTL__DAC_FORCE_DATA__SHIFT 8 -#define DISP_MISC_CNTL 0x00000D00 -#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001 -#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002 -#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004 -#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010 -#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020 -#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040 -#define DISP_MISC_CNTL__SYNC_STRENGTH__MASK 0x00000300 -#define DISP_MISC_CNTL__SYNC_STRENGTH__SHIFT 8 -#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400 -#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000 -#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000 -#define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000 -#define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000 -#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000 -#define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000 -#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN__MASK 0x00F00000 -#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN__SHIFT 20 -#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN__MASK 0x0F000000 -#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN__SHIFT 24 -#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN__MASK 0xF0000000 -#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN__SHIFT 28 -#define DISP_MISC_CNTL__SOFT_RESET_DVO 0x00040000 -#define DISP_MISC_CNTL__SOFT_RESET_TV_R2 0x00000800 -#define DAC_MACRO_CNTL 0x00000D04 -#define DAC_MACRO_CNTL__DAC_WHITE_CNTL__MASK 0x0000000F -#define DAC_MACRO_CNTL__DAC_WHITE_CNTL__SHIFT 0 -#define DAC_MACRO_CNTL__DAC_BG_ADJ__MASK 0x00000F00 -#define DAC_MACRO_CNTL__DAC_BG_ADJ__SHIFT 8 -#define DAC_MACRO_CNTL__DAC_PDWN_R 0x00010000 -#define DAC_MACRO_CNTL__DAC_PDWN_G 0x00020000 -#define DAC_MACRO_CNTL__DAC_PDWN_B 0x00040000 -#define DISP_PWR_MAN 0x00000D08 -#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001 -#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010 -#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS__MASK 0x00000300 -#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS__SHIFT 8 -#define DISP_PWR_MAN_DPMS__ON 0x0 -#define DISP_PWR_MAN_DPMS__STANDBY 0x1 -#define DISP_PWR_MAN_DPMS__SUSPEND 0x2 -#define DISP_PWR_MAN_DPMS__OFF 0x3 -#define DISP_PWR_MAN__DISP_D3_RST 0x00010000 -#define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000 -#define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000 -#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000 -#define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000 -#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000 -#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000 -#define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000 -#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000 -#define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000 -#define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000 -#define DISP_PWR_MAN__DISP_DVO_ENABLE_RST 0x01000000 -#define DISP_MERGE_CNTL 0x00000D60 -#define DISP_MERGE_CNTL__DISP_ALPHA_MODE__MASK 0x00000003 -#define DISP_MERGE_CNTL__DISP_ALPHA_MODE__SHIFT 0 -#define DISP_MERGE_CNTL__DISP_ALPHA_INV 0x00000004 -#define DISP_MERGE_CNTL__DISP_ALPHA_PREMULT 0x00000008 -#define DISP_MERGE_CNTL__DISP_RGB_OFFSET_EN 0x00000100 -#define DISP_MERGE_CNTL__DISP_LIN_TRANS_BYPASS 0x00000200 -#define DISP_MERGE_CNTL__DISP_GRPH_ALPHA__MASK 0x00FF0000 -#define DISP_MERGE_CNTL__DISP_GRPH_ALPHA__SHIFT 16 -#define DISP_MERGE_CNTL__DISP_OV0_ALPHA__MASK 0xFF000000 -#define DISP_MERGE_CNTL__DISP_OV0_ALPHA__SHIFT 24 -#define DISP_OUTPUT_CNTL 0x00000D64 -#define DISP_OUTPUT_CNTL__DISP_DAC_SOURCE__MASK 0x00000003 -#define DISP_OUTPUT_CNTL__DISP_DAC_SOURCE__SHIFT 0 -#define DISP_DAC_SOURCE__YPbPr 0x3 -#define DISP_DAC_SOURCE__PRIMARYCRTC 0x0 -#define DISP_DAC_SOURCE__SECONDARYCRTC 0x1 -#define DISP_DAC_SOURCE__RMX 0x2 -#define DISP_OUTPUT_CNTL__DISP_TRANS_MATRIX_SEL__MASK 0x00000030 -#define DISP_OUTPUT_CNTL__DISP_TRANS_MATRIX_SEL__SHIFT 4 -#define DISP_OUTPUT_CNTL__DISP_RMX_SOURCE 0x00000100 -#define DISP_OUTPUT_CNTL__DISP_RMX_HTAP_SEL 0x00000200 -#define DISP_OUTPUT_CNTL__DISP_RMX_DITH_EN 0x00000400 -#define DISP_OUTPUT_CNTL__DISP_TV_SOURCE 0x00010000 -#define DISP_OUTPUT_CNTL__DISP_TV_MODE__MASK 0x00060000 -#define DISP_OUTPUT_CNTL__DISP_TV_MODE__SHIFT 17 -#define DISP_OUTPUT_CNTL__DISP_TV_YG_DITH_EN 0x00080000 -#define DISP_OUTPUT_CNTL__DISP_TV_CbB_CrR_DITH_EN 0x00100000 -#define DISP_OUTPUT_CNTL__DISP_TV_BIT_WIDTH 0x00200000 -#define DISP_OUTPUT_CNTL__DISP_TV_SYNC_MODE__MASK 0x00C00000 -#define DISP_OUTPUT_CNTL__DISP_TV_SYNC_MODE__SHIFT 22 -#define DISP_OUTPUT_CNTL__DISP_TV_SYNC_FORCE 0x01000000 -#define DISP_OUTPUT_CNTL__DISP_TV_SYNC_COLOR__MASK 0x06000000 -#define DISP_OUTPUT_CNTL__DISP_TV_SYNC_COLOR__SHIFT 25 -#define DISP_OUTPUT_CNTL__DISP_TV_EVEN_FLAG_CNTL__MASK 0x18000000 -#define DISP_OUTPUT_CNTL__DISP_TV_EVEN_FLAG_CNTL__SHIFT 27 -#define DISP_OUTPUT_CNTL__DISP_TV_SYNC_STATUS 0x20000000 -#define DISP_OUTPUT_CNTL__DISP_TV_H_DOWNSCALE 0x40000000 -#define DISP_OUTPUT_CNTL__DISP_TRANS_SOURCE__MASK 0x00003000 -#define DISP_OUTPUT_CNTL__DISP_TRANS_SOURCE__SHIFT 12 -#define DISP_TRANS_SOURCE__PRIMARYCRTC 0x0 -#define DISP_TRANS_SOURCE__SECONDARYCRTC 0x1 -#define DISP_TRANS_SOURCE__RMX 0x2 -#define DISP_OUTPUT_CNTL__DISP_TVDAC_SOURCE__MASK 0x0000000C -#define DISP_OUTPUT_CNTL__DISP_TVDAC_SOURCE__SHIFT 2 -#define DISP_TVDAC_SOURCE__PRIMARYCRTC 0x0 -#define DISP_TVDAC_SOURCE__SECONDARYCRTC 0x1 -#define DISP_TVDAC_SOURCE__RMX 0x2 -#define DISP_TVDAC_SOURCE__YPbPr 0x3 -#define DISP2_MERGE_CNTL 0x00000D68 -#define DISP2_MERGE_CNTL__DISP2_RGB_OFFSET_EN 0x00000100 -#define DAC_EMBEDDED_SYNC_CNTL 0x00000DC0 -#define DAC_EMBEDDED_SYNC_CNTL__DAC_EMBED_SYNC_EN_Y_G 0x00000001 -#define DAC_EMBEDDED_SYNC_CNTL__DAC_EMBED_SYNC_EN_Cb_B 0x00000002 -#define DAC_EMBEDDED_SYNC_CNTL__DAC_EMBED_SYNC_EN_Cr_R 0x00000004 -#define DAC_EMBEDDED_SYNC_CNTL__DAC_TRILEVEL_SYNC_EN 0x00000008 -#define DAC_EMBEDDED_SYNC_CNTL__DAC_EMBED_VSYNC_EN_Y_G 0x00000010 -#define DAC_EMBEDDED_SYNC_CNTL__DAC_EMBED_VSYNC_EN_CbCr_BR 0x00000020 -#define DAC_EMBEDDED_SYNC_CNTL__DAC_HSYNC_WID_LSB__MASK 0x00070000 -#define DAC_EMBEDDED_SYNC_CNTL__DAC_HSYNC_WID_LSB__SHIFT 16 -#define DAC_BROAD_PULSE 0x00000DC4 -#define DAC_BROAD_PULSE__DAC_BROAD_PULSE_START__MASK 0x00001FFF -#define DAC_BROAD_PULSE__DAC_BROAD_PULSE_START__SHIFT 0 -#define DAC_BROAD_PULSE__DAC_BROAD_PULSE_END__MASK 0x1FFF0000 -#define DAC_BROAD_PULSE__DAC_BROAD_PULSE_END__SHIFT 16 -#define DAC_BROAD_PULSE__DAC_BROAD_PULSE_START_R2__MASK 0x00000FFF -#define DAC_BROAD_PULSE__DAC_BROAD_PULSE_START_R2__SHIFT 0 -#define DAC_BROAD_PULSE__DAC_BROAD_PULSE_END_R2__MASK 0x0FFF0000 -#define DAC_BROAD_PULSE__DAC_BROAD_PULSE_END_R2__SHIFT 16 -#define DAC_SKEW_CLKS 0x00000DC8 -#define DAC_SKEW_CLKS__DAC_SKEW_CLKS__MASK 0x000000FF -#define DAC_SKEW_CLKS__DAC_SKEW_CLKS__SHIFT 0 -#define DAC_INCR 0x00000DCC -#define DAC_INCR__DAC_INCR_Y_G__MASK 0x000003FF -#define DAC_INCR__DAC_INCR_Y_G__SHIFT 0 -#define DAC_INCR__DAC_INCR_CrCb_RB__MASK 0x03FF0000 -#define DAC_INCR__DAC_INCR_CrCb_RB__SHIFT 16 -#define DAC_NEG_SYNC_LEVEL 0x00000DD0 -#define DAC_NEG_SYNC_LEVEL__DAC_NEG_SYNC_LEVEL_Y_G__MASK 0x000003FF -#define DAC_NEG_SYNC_LEVEL__DAC_NEG_SYNC_LEVEL_Y_G__SHIFT 0 -#define DAC_NEG_SYNC_LEVEL__DAC_NEG_SYNC_LEVEL_CrCb_RB__MASK 0x03FF0000 -#define DAC_NEG_SYNC_LEVEL__DAC_NEG_SYNC_LEVEL_CrCb_RB__SHIFT 16 -#define DAC_POS_SYNC_LEVEL 0x00000DD4 -#define DAC_POS_SYNC_LEVEL__DAC_POS_SYNC_LEVEL_Y_G__MASK 0x000003FF -#define DAC_POS_SYNC_LEVEL__DAC_POS_SYNC_LEVEL_Y_G__SHIFT 0 -#define DAC_POS_SYNC_LEVEL__DAC_POS_SYNC_LEVEL_CrCb_RB__MASK 0x03FF0000 -#define DAC_POS_SYNC_LEVEL__DAC_POS_SYNC_LEVEL_CrCb_RB__SHIFT 16 -#define DAC_BLANK_LEVEL 0x00000DD8 -#define DAC_BLANK_LEVEL__DAC_BLANK_LEVEL_Y_G__MASK 0x000003FF -#define DAC_BLANK_LEVEL__DAC_BLANK_LEVEL_Y_G__SHIFT 0 -#define DAC_BLANK_LEVEL__DAC_BLANK_LEVEL_CrCb_RB__MASK 0x03FF0000 -#define DAC_BLANK_LEVEL__DAC_BLANK_LEVEL_CrCb_RB__SHIFT 16 -#define DAC_SYNC_EQUALIZATION 0x00000DDC -#define DAC_SYNC_EQUALIZATION__DAC_SYNC_EQ_START__MASK 0x000007FF -#define DAC_SYNC_EQUALIZATION__DAC_SYNC_EQ_START__SHIFT 0 -#define DAC_SYNC_EQUALIZATION__DAC_SYNC_EQ_END__MASK 0x07FF0000 -#define DAC_SYNC_EQUALIZATION__DAC_SYNC_EQ_END__SHIFT 16 -#define TV_MASTER_CNTL 0x00000800 -#define TV_MASTER_CNTL__TV_ASYNC_RST 0x00000001 -#define TV_MASTER_CNTL__CRT_ASYNC_RST 0x00000002 -#define TV_MASTER_CNTL__RESTART_PHASE_FIX 0x00000008 -#define TV_MASTER_CNTL__TV_FIFO_ASYNC_RST 0x00000010 -#define TV_MASTER_CNTL__MV_BP_LEVEL_FIX_EN 0x00000020 -#define TV_MASTER_CNTL__EXTRA_BIT_ONE_0 0x00000040 -#define TV_MASTER_CNTL__CRT_FIFO_CE_EN 0x00000200 -#define TV_MASTER_CNTL__TV_FIFO_CE_EN 0x00000400 -#define TV_MASTER_CNTL__RE_SYNC_NOW_SEL__MASK 0x0000C000 -#define TV_MASTER_CNTL__RE_SYNC_NOW_SEL__SHIFT 14 -#define TV_MASTER_CNTL__EXTRA_BIT_ZERO_1 0x00010000 -#define TV_MASTER_CNTL__EXTRA_BIT_ONE_1 0x00020000 -#define TV_MASTER_CNTL__EXTRA_BIT_ZERO_2 0x00040000 -#define TV_MASTER_CNTL__EXTRA_BIT_ONE_2 0x00080000 -#define TV_MASTER_CNTL__TVCLK_ALWAYS_ONb 0x40000000 -#define TV_MASTER_CNTL__TV_ON 0x80000000 -#define TV_DAC_CNTL 0x0000088C -#define TV_DAC_CNTL__NBLANK 0x00000001 -#define TV_DAC_CNTL__NHOLD 0x00000002 -#define TV_DAC_CNTL__PEDESTAL 0x00000004 -#define TV_DAC_CNTL__DETECT 0x00000010 -#define TV_DAC_CNTL__CMPOUT 0x00000020 -#define TV_DAC_CNTL__BGSLEEP 0x00000040 -#define TV_DAC_CNTL__STD__MASK 0x00000300 -#define TV_DAC_CNTL__STD__SHIFT 8 -#define STD__PAL 0x0 -#define STD__NTSC 0x1 -#define STD__PS2 0x2 -#define STD__RS343 0x3 -#define TV_DAC_CNTL__MON__MASK 0x0000F000 -#define TV_DAC_CNTL__MON__SHIFT 12 -#define TV_DAC_CNTL__BGADJ__MASK 0x000F0000 -#define TV_DAC_CNTL__BGADJ__SHIFT 16 -#define TV_DAC_CNTL__DACADJ__MASK 0x00F00000 -#define TV_DAC_CNTL__DACADJ__SHIFT 20 -#define TV_DAC_CNTL__RDACPD 0x01000000 -#define TV_DAC_CNTL__GDACPD 0x02000000 -#define TV_DAC_CNTL__BDACPD 0x04000000 -#define TV_DAC_CNTL__RDACDET 0x20000000 -#define TV_DAC_CNTL__GDACDET 0x40000000 -#define TV_DAC_CNTL__BDACDET 0x80000000 -#define TV_DAC_CNTL__DACADJ_R4__MASK 0x01F00000 -#define TV_DAC_CNTL__DACADJ_R4__SHIFT 20 -#define TV_DAC_CNTL__RDACPD_R4 0x02000000 -#define TV_DAC_CNTL__GDACPD_R4 0x04000000 -#define TV_DAC_CNTL__BDACPD_R4 0x08000000 -#define TV_DAC_CNTL__TVENABLE_R4 0x10000000 -#define VIPPAD_EN 0x000001A0 -#define VIPPAD_EN__VIPPAD_EN__MASK 0x0007FFFF -#define VIPPAD_EN__VIPPAD_EN__SHIFT 0 -#define VIPPAD_EN__VIPPAD_EN_TVODATA__MASK 0x000003FF -#define VIPPAD_EN__VIPPAD_EN_TVODATA__SHIFT 0 -#define VIPPAD_EN__VIPPAD_EN_TVOCLKO 0x00000400 -#define VIPPAD_EN__VIPPAD_EN_ROMCSb 0x00000800 -#define VIPPAD_EN__VIPPAD_EN_VHAD__MASK 0x00003000 -#define VIPPAD_EN__VIPPAD_EN_VHAD__SHIFT 12 -#define VIPPAD_EN__VIPPAD_EN_VPHCTL 0x00010000 -#define VIPPAD_EN__VIPPAD_EN_VIPCLK 0x00020000 -#define VIPPAD_EN__VIPPAD_EN_SI 0x00080000 -#define VIPPAD_EN__VIPPAD_EN_SO 0x00100000 -#define VIPPAD_EN__VIPPAD_EN_SCK 0x00200000 -#define VIPPAD_Y 0x000001A4 -#define VIPPAD_Y__VIPPAD_Y__MASK 0x0007FFFF -#define VIPPAD_Y__VIPPAD_Y__SHIFT 0 -#define VIPPAD_Y__VIPPAD_Y_TVODATA__MASK 0x000003FF -#define VIPPAD_Y__VIPPAD_Y_TVODATA__SHIFT 0 -#define VIPPAD_Y__VIPPAD_Y_TVOCLKO 0x00000400 -#define VIPPAD_Y__VIPPAD_Y_ROMCSb 0x00000800 -#define VIPPAD_Y__VIPPAD_Y_VHAD__MASK 0x00003000 -#define VIPPAD_Y__VIPPAD_Y_VHAD__SHIFT 12 -#define VIPPAD_Y__VIPPAD_Y_VPHCTL 0x00010000 -#define VIPPAD_Y__VIPPAD_Y_VIPCLK 0x00020000 -#define VIPPAD_Y__VIPPAD_Y_SI 0x00080000 -#define VIPPAD_Y__VIPPAD_Y_SO 0x00100000 -#define VIPPAD_Y__VIPPAD_Y_SCK 0x00200000 -#define VIPPAD1_EN 0x000001B0 -#define VIPPAD1_EN__VIPPAD1_EN__MASK 0x0003FFFF -#define VIPPAD1_EN__VIPPAD1_EN__SHIFT 0 -#define VIPPAD1_EN__VIPPAD_EN_VID__MASK 0x000000FF -#define VIPPAD1_EN__VIPPAD_EN_VID__SHIFT 0 -#define VIPPAD1_EN__VIPPAD_EN_VPCLK0 0x00000100 -#define VIPPAD1_EN__VIPPAD_EN_DVALID 0x00000200 -#define VIPPAD1_EN__VIPPAD_EN_PSYNC 0x00000400 -#define VIPPAD1_EN__VIPPAD_EN_DVODATA__MASK 0x0FFF0000 -#define VIPPAD1_EN__VIPPAD_EN_DVODATA__SHIFT 16 -#define VIPPAD1_EN__VIPPAD_EN_DVOCNTL__MASK 0x70000000 -#define VIPPAD1_EN__VIPPAD_EN_DVOCNTL__SHIFT 28 -#define VIPPAD1_Y 0x000001B4 -#define VIPPAD1_Y__VIPPAD1_Y__MASK 0x0003FFFF -#define VIPPAD1_Y__VIPPAD1_Y__SHIFT 0 -#define VIPPAD1_Y__VIPPAD_Y_VID__MASK 0x000000FF -#define VIPPAD1_Y__VIPPAD_Y_VID__SHIFT 0 -#define VIPPAD1_Y__VIPPAD_Y_VPCLK0 0x00000100 -#define VIPPAD1_Y__VIPPAD_Y_DVALID 0x00000200 -#define VIPPAD1_Y__VIPPAD_Y_PSYNC 0x00000400 -#define VIPPAD1_Y__VIPPAD_Y_DVODATA__MASK 0x0FFF0000 -#define VIPPAD1_Y__VIPPAD_Y_DVODATA__SHIFT 16 -#define VIPPAD1_Y__VIPPAD_Y_DVOCNTL__MASK 0x70000000 -#define VIPPAD1_Y__VIPPAD_Y_DVOCNTL__SHIFT 28 -#define GPIO_DDC1 0x00000060 -#define GPIO_DDC1__DDC1_DATA_OUTPUT 0x00000001 -#define GPIO_DDC1__DDC1_CLK_OUTPUT 0x00000002 -#define GPIO_DDC1__DDC1_DATA_INPUT 0x00000100 -#define GPIO_DDC1__DDC1_CLK_INPUT 0x00000200 -#define GPIO_DDC1__DDC1_DATA_OUT_EN 0x00010000 -#define GPIO_DDC1__DDC1_CLK_OUT_EN 0x00020000 -#define GPIO_DDC1__SW_WANTS_TO_USE_DVI_I2C 0x00100000 -#define GPIO_DDC1__SW_CAN_USE_DVI_I2C 0x00100000 -#define GPIO_DDC1__SW_DONE_USING_DVI_I2C 0x00200000 -#define GPIO_DDC1__HW_USING_DVI_I2C 0x00400000 -#define GPIO_DDC2 0x00000064 -#define GPIO_DDC2__DDC2_DATA_OUTPUT 0x00000001 -#define GPIO_DDC2__DDC2_CLK_OUTPUT 0x00000002 -#define GPIO_DDC2__DDC2_DATA_INPUT 0x00000100 -#define GPIO_DDC2__DDC2_CLK_INPUT 0x00000200 -#define GPIO_DDC2__DDC2_DATA_OUT_EN 0x00010000 -#define GPIO_DDC2__DDC2_CLK_OUT_EN 0x00020000 -#define GPIO_DDC2__SW_WANTS_TO_USE_DVI_I2C 0x00100000 -#define GPIO_DDC2__SW_CAN_USE_DVI_I2C 0x00100000 -#define GPIO_DDC2__SW_DONE_USING_DVI_I2C 0x00200000 -#define GPIO_DDC2__HW_USING_DVI_I2C 0x00400000 -#define GPIO_DVI_DDC 0x00000064 -#define GPIO_DVI_DDC__DVI_DDC_DATA_OUTPUT 0x00000001 -#define GPIO_DVI_DDC__DVI_DCC_DATA_OUTPUT 0x00000001 -#define GPIO_DVI_DDC__DVI_DDC_CLK_OUTPUT 0x00000002 -#define GPIO_DVI_DDC__DVI_DDC_DATA_INPUT 0x00000100 -#define GPIO_DVI_DDC__DVI_DDC_CLK_INPUT 0x00000200 -#define GPIO_DVI_DDC__DVI_DDC_DATA_OUT_EN 0x00010000 -#define GPIO_DVI_DDC__DVI_DDC_CLK_OUT_EN 0x00020000 -#define GPIO_DVI_DDC__SW_WANTS_TO_USE_DVI_I2C 0x00100000 -#define GPIO_DVI_DDC__SW_CAN_USE_DVI_I2C 0x00100000 -#define GPIO_DVI_DDC__SW_DONE_USING_DVI_I2C 0x00200000 -#define GPIO_DVI_DDC__HW_USING_DVI_I2C 0x00400000 -#define GPIO_MONID 0x00000068 -#define GPIO_MONID__GPIO_MONID_0_OUTPUT 0x00000001 -#define GPIO_MONID__GPIO_MONID_1_OUTPUT 0x00000002 -#define GPIO_MONID__GPIO_MONID_0_INPUT 0x00000100 -#define GPIO_MONID__GPIO_MONID_1_INPUT 0x00000200 -#define GPIO_MONID__GPIO_MONID_0_OUT_EN 0x00010000 -#define GPIO_MONID__GPIO_MONID_1_OUT_EN 0x00020000 -#define GPIO_CRT2_DDC 0x0000006C -#define GPIO_CRT2_DDC__CRT2_DDC_DATA_OUTPUT 0x00000001 -#define GPIO_CRT2_DDC__CRT2_DDC_CLK_OUTPUT 0x00000002 -#define GPIO_CRT2_DDC__CRT2_DDC_DATA_INPUT 0x00000100 -#define GPIO_CRT2_DDC__CRT2_DDC_CLK_INPUT 0x00000200 -#define GPIO_CRT2_DDC__CRT2_DDC_DATA_OUT_EN 0x00010000 -#define GPIO_CRT2_DDC__CRT2_DDC_CLK_OUT_EN 0x00020000 -#define CLOCK_CNTL_INDEX 0x00000008 -#define CLOCK_CNTL_INDEX__PLL_ADDR__MASK 0x0000001F -#define CLOCK_CNTL_INDEX__PLL_ADDR__SHIFT 0 -#define CLOCK_CNTL_INDEX__PLL_WR_EN 0x00000080 -#define CLOCK_CNTL_INDEX__PPLL_DIV_SEL__MASK 0x00000300 -#define CLOCK_CNTL_INDEX__PPLL_DIV_SEL__SHIFT 8 -#define CLOCK_CNTL_INDEX__PLL_ADDR_R2__MASK 0x0000003F -#define CLOCK_CNTL_INDEX__PLL_ADDR_R2__SHIFT 0 -#define CLOCK_CNTL_DATA 0x0000000C -#define CLOCK_CNTL_DATA__PLL_DATA__MASK 0xFFFFFFFF -#define CLOCK_CNTL_DATA__PLL_DATA__SHIFT 0 -#define MCLK_CNTL 0x00000012 -#define MCLK_CNTL__MCLKA_SRC_SEL__MASK 0x00000007 -#define MCLK_CNTL__MCLKA_SRC_SEL__SHIFT 0 -#define MCLK_CNTL__YCLKA_SRC_SEL__MASK 0x00000070 -#define MCLK_CNTL__YCLKA_SRC_SEL__SHIFT 4 -#define MCLK_CNTL__MCLKB_SRC_SEL__MASK 0x00000700 -#define MCLK_CNTL__MCLKB_SRC_SEL__SHIFT 8 -#define MCLK_CNTL__YCLKB_SRC_SEL__MASK 0x00007000 -#define MCLK_CNTL__YCLKB_SRC_SEL__SHIFT 12 -#define MCLK_CNTL__FORCE_MCLKA 0x00010000 -#define MCLK_CNTL__FORCE_MCLKB 0x00020000 -#define MCLK_CNTL__FORCE_YCLKA 0x00040000 -#define MCLK_CNTL__FORCE_YCLKB 0x00080000 -#define MCLK_CNTL__FORCE_MC 0x00100000 -#define MCLK_CNTL__FORCE_AIC 0x00200000 -#define MCLK_CNTL__MRDCKA0_SOUTSEL__MASK 0x03000000 -#define MCLK_CNTL__MRDCKA0_SOUTSEL__SHIFT 24 -#define MCLK_CNTL__MRDCKA1_SOUTSEL__MASK 0x0C000000 -#define MCLK_CNTL__MRDCKA1_SOUTSEL__SHIFT 26 -#define MCLK_CNTL__MRDCKB0_SOUTSEL__MASK 0x30000000 -#define MCLK_CNTL__MRDCKB0_SOUTSEL__SHIFT 28 -#define MCLK_CNTL__MRDCKB1_SOUTSEL__MASK 0xC0000000 -#define MCLK_CNTL__MRDCKB1_SOUTSEL__SHIFT 30 -#define MCLK_CNTL__FORCE_MC_MCLKA 0x00010000 -#define MCLK_CNTL__FORCE_MC_MCLKB 0x00020000 -#define MCLK_CNTL__FORCE_MC_MCLK 0x00100000 -#define MCLK_CNTL__DISABLE_MC_MCLKA 0x00200000 -#define MCLK_CNTL__DISABLE_MC_MCLKB 0x00400000 -#define SCLK_CNTL 0x0000000D -#define SCLK_CNTL__SCLK_SRC_SEL__MASK 0x00000007 -#define SCLK_CNTL__SCLK_SRC_SEL__SHIFT 0 -#define SCLK_CNTL__TCLK_SRC_SEL__MASK 0x00000700 -#define SCLK_CNTL__TCLK_SRC_SEL__SHIFT 8 -#define SCLK_CNTL__FORCE_CP 0x00010000 -#define SCLK_CNTL__FORCE_HDP 0x00020000 -#define SCLK_CNTL__FORCE_DISP 0x00040000 -#define SCLK_CNTL__FORCE_TOP 0x00080000 -#define SCLK_CNTL__FORCE_E2 0x00100000 -#define SCLK_CNTL__FORCE_SE 0x00200000 -#define SCLK_CNTL__FORCE_IDCT 0x00400000 -#define SCLK_CNTL__FORCE_VIP 0x00800000 -#define SCLK_CNTL__FORCE_RE 0x01000000 -#define SCLK_CNTL__FORCE_PB 0x02000000 -#define SCLK_CNTL__FORCE_TAM 0x04000000 -#define SCLK_CNTL__FORCE_TDM 0x08000000 -#define SCLK_CNTL__FORCE_RB 0x10000000 -#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008 -#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010 -#define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040 -#define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080 -#define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100 -#define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200 -#define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400 -#define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800 -#define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000 -#define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000 -#define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000 -#define SCLK_CNTL__FORCE_DISP2 0x00008000 -#define SCLK_CNTL__FORCE_DISP1 0x00040000 -#define SCLK_CNTL__FORCE_SUBPIC 0x40000000 -#define SCLK_CNTL__FORCE_OV0 0x80000000 -#define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020 -#define SCLK_CNTL__FORCE_TV_SCLK 0x20000000 -#define SCLK_CNTL__VAP_MAX_DYN_STOP_LAT 0x00000080 -#define SCLK_CNTL__SR_MAX_DYN_STOP_LAT 0x00000400 -#define SCLK_CNTL__PX_MAX_DYN_STOP_LAT 0x00000800 -#define SCLK_CNTL__TX_MAX_DYN_STOP_LAT 0x00001000 -#define SCLK_CNTL__US_MAX_DYN_STOP_LAT 0x00002000 -#define SCLK_CNTL__SU_MAX_DYN_STOP_LAT 0x00004000 -#define SCLK_CNTL__FORCE_VAP 0x00200000 -#define SCLK_CNTL__FORCE_SR 0x02000000 -#define SCLK_CNTL__FORCE_PX 0x04000000 -#define SCLK_CNTL__FORCE_TX 0x08000000 -#define SCLK_CNTL__FORCE_US 0x10000000 -#define SCLK_CNTL__FORCE_SU 0x40000000 -#define PPLL_CNTL 0x00000002 -#define PPLL_CNTL__PPLL_RESET 0x00000001 -#define PPLL_CNTL__PPLL_SLEEP 0x00000002 -#define PPLL_CNTL__PPLL_TST_EN 0x00000004 -#define PPLL_CNTL__PPLL_REFCLK_SEL 0x00000010 -#define PPLL_CNTL__PPLL_FBCLK_SEL 0x00000020 -#define PPLL_CNTL__PPLL_TCPOFF 0x00000040 -#define PPLL_CNTL__PPLL_TVCOMAX 0x00000080 -#define PPLL_CNTL__PPLL_PCP__MASK 0x00000700 -#define PPLL_CNTL__PPLL_PCP__SHIFT 8 -#define PPLL_CNTL__PPLL_PVG__MASK 0x00003800 -#define PPLL_CNTL__PPLL_PVG__SHIFT 11 -#define PPLL_CNTL__PPLL_PDC__MASK 0x0000C000 -#define PPLL_CNTL__PPLL_PDC__SHIFT 14 -#define PPLL_CNTL__PPLL_ATOMIC_UPDATE_EN 0x00010000 -#define PPLL_CNTL__PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000 -#define PPLL_CNTL__PPLL_ATOMIC_UPDATE_SYNC 0x00040000 -#define PPLL_CNTL__PPLL_DISABLE_AUTO_RESET 0x00080000 -#define PPLL_CNTL__PPLL_DIV_RESET 0x00000008 -#define PPLL_REF_DIV 0x00000003 -#define PPLL_REF_DIV__PPLL_REF_DIV__MASK 0x000003FF -#define PPLL_REF_DIV__PPLL_REF_DIV__SHIFT 0 -#define PPLL_REF_DIV__PPLL_ATOMIC_UPDATE_W 0x00008000 -#define PPLL_REF_DIV__PPLL_ATOMIC_UPDATE_R 0x00008000 -#define PPLL_REF_DIV__PPLL_REF_DIV_SRC__MASK 0x00030000 -#define PPLL_REF_DIV__PPLL_REF_DIV_SRC__SHIFT 16 -#define PPLL_REF_DIV_SRC__XTALIN 0x0 -#define PPLL_REF_DIV_SRC__PLLSCLK_2 0x1 -#define PPLL_REF_DIV_SRC__PLLSCLK_4 0x2 -#define PPLL_REF_DIV_SRC__SREFCLK 0x3 -#define PPLL_REF_DIV__PPLL_REF_DIV_ACC__MASK 0x0FFC0000 -#define PPLL_REF_DIV__PPLL_REF_DIV_ACC__SHIFT 18 -#define PPLL_DIV_0 0x00000004 -#define PPLL_DIV_0__PPLL_FB0_DIV__MASK 0x000007FF -#define PPLL_DIV_0__PPLL_FB0_DIV__SHIFT 0 -#define PPLL_DIV_0__PPLL_ATOMIC_UPDATE_W 0x00008000 -#define PPLL_DIV_0__PPLL_ATOMIC_UPDATE_R 0x00008000 -#define PPLL_DIV_0__PPLL_POST0_DIV__MASK 0x00070000 -#define PPLL_DIV_0__PPLL_POST0_DIV__SHIFT 16 -#define PPLL_DIV_0__PPLL_FB_DIV_FRACTION__MASK 0x00380000 -#define PPLL_DIV_0__PPLL_FB_DIV_FRACTION__SHIFT 19 -#define PPLL_DIV_0__PPLL_FB_DIV_FRACTION_UPDATE 0x00400000 -#define PPLL_DIV_0__PPLL_FB_DIV_FRACTION_EN 0x00800000 -#define PPLL_DIV_1 0x00000005 -#define PPLL_DIV_1__PPLL_FB1_DIV__MASK 0x000007FF -#define PPLL_DIV_1__PPLL_FB1_DIV__SHIFT 0 -#define PPLL_DIV_1__PPLL_ATOMIC_UPDATE_W 0x00008000 -#define PPLL_DIV_1__PPLL_ATOMIC_UPDATE_R 0x00008000 -#define PPLL_DIV_1__PPLL_POST1_DIV__MASK 0x00070000 -#define PPLL_DIV_1__PPLL_POST1_DIV__SHIFT 16 -#define PPLL_DIV_2 0x00000006 -#define PPLL_DIV_2__PPLL_FB2_DIV__MASK 0x000007FF -#define PPLL_DIV_2__PPLL_FB2_DIV__SHIFT 0 -#define PPLL_DIV_2__PPLL_ATOMIC_UPDATE_W 0x00008000 -#define PPLL_DIV_2__PPLL_ATOMIC_UPDATE_R 0x00008000 -#define PPLL_DIV_2__PPLL_POST2_DIV__MASK 0x00070000 -#define PPLL_DIV_2__PPLL_POST2_DIV__SHIFT 16 -#define PPLL_DIV_3 0x00000007 -#define PPLL_DIV_3__PPLL_FB3_DIV__MASK 0x000007FF -#define PPLL_DIV_3__PPLL_FB3_DIV__SHIFT 0 -#define PPLL_DIV_3__PPLL_ATOMIC_UPDATE_W 0x00008000 -#define PPLL_DIV_3__PPLL_ATOMIC_UPDATE_R 0x00008000 -#define PPLL_DIV_3__PPLL_POST3_DIV__MASK 0x00070000 -#define PPLL_DIV_3__PPLL_POST3_DIV__SHIFT 16 -#define VCLK_ECP_CNTL 0x00000008 -#define VCLK_ECP_CNTL__VCLK_SRC_SEL__MASK 0x00000003 -#define VCLK_ECP_CNTL__VCLK_SRC_SEL__SHIFT 0 -#define VCLK_SRC_SEL__CPUCLK 0x0 -#define VCLK_SRC_SEL__PSCANCLK 0x1 -#define VCLK_SRC_SEL__BYTE_CLK 0x2 -#define VCLK_SRC_SEL__PPLLCLK 0x3 -#define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010 -#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040 -#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080 -#define VCLK_ECP_CNTL__ECP_DIV__MASK 0x00000300 -#define VCLK_ECP_CNTL__ECP_DIV__SHIFT 8 -#define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000 -#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000 -#define VCLK_ECP_CNTL__BYTE_CLK_POST_DIV__MASK 0x00030000 -#define VCLK_ECP_CNTL__BYTE_CLK_POST_DIV__SHIFT 16 -#define VCLK_ECP_CNTL__BYTE_CLK_OUT_EN 0x00100000 -#define VCLK_ECP_CNTL__BYTE_CLK_SKEW__MASK 0x07000000 -#define VCLK_ECP_CNTL__BYTE_CLK_SKEW__SHIFT 24 -#define VCLK_ECP_CNTL__PCICLK_INVERT 0x00000020 -#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020 -#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT_R3 0x08000000 -#define VCLK_ECP_CNTL__DISP_DAC_PIXCLK_DAC_BLANK_OFF 0x00800000 -#define HTOTAL_CNTL 0x00000009 -#define HTOTAL_CNTL__HTOT_PIX_SLIP__MASK 0x0000000F -#define HTOTAL_CNTL__HTOT_PIX_SLIP__SHIFT 0 -#define HTOTAL_CNTL__HTOT_VCLK_SLIP__MASK 0x00000F00 -#define HTOTAL_CNTL__HTOT_VCLK_SLIP__SHIFT 8 -#define HTOTAL_CNTL__HTOT_PPLL_SLIP__MASK 0x00070000 -#define HTOTAL_CNTL__HTOT_PPLL_SLIP__SHIFT 16 -#define HTOTAL_CNTL__HTOT_CNTL_EDGE 0x01000000 -#define HTOTAL_CNTL__HTOT_CNTL_VGA_EN 0x10000000 -#define FP_H_SYNC_STRT_WID 0x000002C4 -#define FP_H_SYNC_STRT_WID__FP_H_SYNC_STRT_PIX__MASK 0x00000007 -#define FP_H_SYNC_STRT_WID__FP_H_SYNC_STRT_PIX__SHIFT 0 -#define FP_H_SYNC_STRT_WID__FP_H_SYNC_STRT_CHAR__MASK 0x00001FF8 -#define FP_H_SYNC_STRT_WID__FP_H_SYNC_STRT_CHAR__SHIFT 3 -#define FP_H_SYNC_STRT_WID__FP_H_SYNC_WID__MASK 0x003F0000 -#define FP_H_SYNC_STRT_WID__FP_H_SYNC_WID__SHIFT 16 -#define FP_H_SYNC_STRT_WID__FP_H_SYNC_POL 0x00800000 -#define FP_V_SYNC_STRT_WID 0x000002C8 -#define FP_V_SYNC_STRT_WID__FP_V_SYNC_STRT__MASK 0x00000FFF -#define FP_V_SYNC_STRT_WID__FP_V_SYNC_STRT__SHIFT 0 -#define FP_V_SYNC_STRT_WID__FP_V_SYNC_WID__MASK 0x001F0000 -#define FP_V_SYNC_STRT_WID__FP_V_SYNC_WID__SHIFT 16 -#define FP_V_SYNC_STRT_WID__FP_V_SYNC_POL 0x00800000 -#define FP_CRTC_H_TOTAL_DISP 0x00000250 -#define FP_CRTC_H_TOTAL_DISP__FP_CRTC_H_TOTAL__MASK 0x000003FF -#define FP_CRTC_H_TOTAL_DISP__FP_CRTC_H_TOTAL__SHIFT 0 -#define FP_CRTC_H_TOTAL_DISP__FP_CRTC_H_DISP__MASK 0x01FF0000 -#define FP_CRTC_H_TOTAL_DISP__FP_CRTC_H_DISP__SHIFT 16 -#define FP_CRTC_V_TOTAL_DISP 0x00000254 -#define FP_CRTC_V_TOTAL_DISP__FP_CRTC_V_TOTAL__MASK 0x00000FFF -#define FP_CRTC_V_TOTAL_DISP__FP_CRTC_V_TOTAL__SHIFT 0 -#define FP_CRTC_V_TOTAL_DISP__FP_CRTC_V_DISP__MASK 0x0FFF0000 -#define FP_CRTC_V_TOTAL_DISP__FP_CRTC_V_DISP__SHIFT 16 -#define PALETTE_INDEX 0x000000B0 -#define PALETTE_INDEX__PALETTE_W_INDEX__MASK 0x000000FF -#define PALETTE_INDEX__PALETTE_W_INDEX__SHIFT 0 -#define PALETTE_INDEX__PALETTE_R_INDEX__MASK 0x00FF0000 -#define PALETTE_INDEX__PALETTE_R_INDEX__SHIFT 16 -#define PALETTE_DATA 0x000000B4 -#define PALETTE_DATA__PALETTE_DATA_B__MASK 0x000000FF -#define PALETTE_DATA__PALETTE_DATA_B__SHIFT 0 -#define PALETTE_DATA__PALETTE_DATA_G__MASK 0x0000FF00 -#define PALETTE_DATA__PALETTE_DATA_G__SHIFT 8 -#define PALETTE_DATA__PALETTE_DATA_R__MASK 0x00FF0000 -#define PALETTE_DATA__PALETTE_DATA_R__SHIFT 16 -#define PALETTE_30_DATA 0x000000B8 -#define PALETTE_30_DATA__PALETTE_DATA_B__MASK 0x000003FF -#define PALETTE_30_DATA__PALETTE_DATA_B__SHIFT 0 -#define PALETTE_30_DATA__PALETTE_DATA_G__MASK 0x000FFC00 -#define PALETTE_30_DATA__PALETTE_DATA_G__SHIFT 10 -#define PALETTE_30_DATA__PALETTE_DATA_R__MASK 0x3FF00000 -#define PALETTE_30_DATA__PALETTE_DATA_R__SHIFT 20 -#define SURFACE_CNTL 0x00000B00 -#define SURFACE_CNTL__SURF_TRANSLATION_DIS 0x00000100 -#define SURFACE_CNTL__NONSURF_AP0_SWP__MASK 0x00300000 -#define SURFACE_CNTL__NONSURF_AP0_SWP__SHIFT 20 -#define SURFACE_CNTL__NONSURF_AP1_SWP__MASK 0x00C00000 -#define SURFACE_CNTL__NONSURF_AP1_SWP__SHIFT 22 -#define SURFACE0_INFO 0x00000B0C -#define SURFACE0_INFO__SURF0_PITCHSEL__MASK 0x000003FF -#define SURFACE0_INFO__SURF0_PITCHSEL__SHIFT 0 -#define SURFACE0_INFO__SURF0_TILE_MODE__MASK 0x00030000 -#define SURFACE0_INFO__SURF0_TILE_MODE__SHIFT 16 -#define SURF0_TILE_MODE__NO_TILING(p) 0x0 -#define SURF0_TILE_MODE__MACRO_TILING(p) 0x0 -#define SURF0_TILE_MODE__MICRO_TILING(p) 0x0 -#define SURF0_TILE_MODE__MACRO_MICRO_TILING(p) 0x0 -#define SURF0_TILE_MODE__32_BIT_Z_TILING(p) 0x0 -#define SURF0_TILE_MODE__16_BIT_Z_TILING(p) 0x0 -#define SURFACE0_INFO__SURF0_AP0_SWP__MASK 0x00300000 -#define SURFACE0_INFO__SURF0_AP0_SWP__SHIFT 20 -#define SURFACE0_INFO__SURF0_AP1_SWP__MASK 0x00C00000 -#define SURFACE0_INFO__SURF0_AP1_SWP__SHIFT 22 -#define SURFACE0_INFO__SURF0_WRITE_FLAG 0x01000000 -#define SURFACE0_INFO__SURF0_READ_FLAG 0x02000000 -#define SURFACE0_INFO__SURF0_TILE_MODE_R2__MASK 0x00070000 -#define SURFACE0_INFO__SURF0_TILE_MODE_R2__SHIFT 16 -#define SURFACE0_INFO__SURF0_PITCHSEL_R3__MASK 0x00001FFF -#define SURFACE0_INFO__SURF0_PITCHSEL_R3__SHIFT 0 -#define SURFACE0_LOWER_BOUND 0x00000B04 -#define SURFACE0_LOWER_BOUND__SURF_LOWER__MASK 0x0FFFFFFF -#define SURFACE0_LOWER_BOUND__SURF_LOWER__SHIFT 0 -#define SURFACE0_UPPER_BOUND 0x00000B08 -#define SURFACE0_UPPER_BOUND__SURF_UPPER__MASK 0x0FFFFFFF -#define SURFACE0_UPPER_BOUND__SURF_UPPER__SHIFT 0 -#define SURFACE1_INFO 0x00000B1C -#define SURFACE1_INFO__SURF1_PITCHSEL__MASK 0x000003FF -#define SURFACE1_INFO__SURF1_PITCHSEL__SHIFT 0 -#define SURFACE1_INFO__SURF1_TILE_MODE__MASK 0x00030000 -#define SURFACE1_INFO__SURF1_TILE_MODE__SHIFT 16 -#define SURFACE1_INFO__SURF1_AP0_SWP__MASK 0x00300000 -#define SURFACE1_INFO__SURF1_AP0_SWP__SHIFT 20 -#define SURFACE1_INFO__SURF1_AP1_SWP__MASK 0x00C00000 -#define SURFACE1_INFO__SURF1_AP1_SWP__SHIFT 22 -#define SURFACE1_INFO__SURF1_WRITE_FLAG 0x01000000 -#define SURFACE1_INFO__SURF1_READ_FLAG 0x02000000 -#define SURFACE1_INFO__SURF1_TILE_MODE_R2__MASK 0x00070000 -#define SURFACE1_INFO__SURF1_TILE_MODE_R2__SHIFT 16 -#define SURFACE1_INFO__SURF1_PITCHSEL_R3__MASK 0x00001FFF -#define SURFACE1_INFO__SURF1_PITCHSEL_R3__SHIFT 0 -#define SURFACE1_LOWER_BOUND 0x00000B14 -#define SURFACE1_LOWER_BOUND__SURF_LOWER__MASK 0x0FFFFFFF -#define SURFACE1_LOWER_BOUND__SURF_LOWER__SHIFT 0 -#define SURFACE1_UPPER_BOUND 0x00000B18 -#define SURFACE1_UPPER_BOUND__SURF_UPPER__MASK 0x0FFFFFFF -#define SURFACE1_UPPER_BOUND__SURF_UPPER__SHIFT 0 -#define SURFACE2_INFO 0x00000B2C -#define SURFACE2_INFO__SURF2_PITCHSEL__MASK 0x000003FF -#define SURFACE2_INFO__SURF2_PITCHSEL__SHIFT 0 -#define SURFACE2_INFO__SURF2_TILE_MODE__MASK 0x00030000 -#define SURFACE2_INFO__SURF2_TILE_MODE__SHIFT 16 -#define SURFACE2_INFO__SURF2_AP0_SWP__MASK 0x00300000 -#define SURFACE2_INFO__SURF2_AP0_SWP__SHIFT 20 -#define SURFACE2_INFO__SURF2_AP1_SWP__MASK 0x00C00000 -#define SURFACE2_INFO__SURF2_AP1_SWP__SHIFT 22 -#define SURFACE2_INFO__SURF2_WRITE_FLAG 0x01000000 -#define SURFACE2_INFO__SURF2_READ_FLAG 0x02000000 -#define SURFACE2_INFO__SURF2_TILE_MODE_R2__MASK 0x00070000 -#define SURFACE2_INFO__SURF2_TILE_MODE_R2__SHIFT 16 -#define SURFACE2_INFO__SURF2_PITCHSEL_R3__MASK 0x00001FFF -#define SURFACE2_INFO__SURF2_PITCHSEL_R3__SHIFT 0 -#define SURFACE2_LOWER_BOUND 0x00000B24 -#define SURFACE2_LOWER_BOUND__SURF_LOWER__MASK 0x0FFFFFFF -#define SURFACE2_LOWER_BOUND__SURF_LOWER__SHIFT 0 -#define SURFACE2_UPPER_BOUND 0x00000B28 -#define SURFACE2_UPPER_BOUND__SURF_UPPER__MASK 0x0FFFFFFF -#define SURFACE2_UPPER_BOUND__SURF_UPPER__SHIFT 0 -#define SURFACE3_INFO 0x00000B3C -#define SURFACE3_INFO__SURF3_PITCHSEL__MASK 0x000003FF -#define SURFACE3_INFO__SURF3_PITCHSEL__SHIFT 0 -#define SURFACE3_INFO__SURF3_TILE_MODE__MASK 0x00030000 -#define SURFACE3_INFO__SURF3_TILE_MODE__SHIFT 16 -#define SURFACE3_INFO__SURF3_AP0_SWP__MASK 0x00300000 -#define SURFACE3_INFO__SURF3_AP0_SWP__SHIFT 20 -#define SURFACE3_INFO__SURF3_AP1_SWP__MASK 0x00C00000 -#define SURFACE3_INFO__SURF3_AP1_SWP__SHIFT 22 -#define SURFACE3_INFO__SURF3_WRITE_FLAG 0x01000000 -#define SURFACE3_INFO__SURF3_READ_FLAG 0x02000000 -#define SURFACE3_INFO__SURF3_TILE_MODE_R2__MASK 0x00070000 -#define SURFACE3_INFO__SURF3_TILE_MODE_R2__SHIFT 16 -#define SURFACE3_INFO__SURF3_PITCHSEL_R3__MASK 0x00001FFF -#define SURFACE3_INFO__SURF3_PITCHSEL_R3__SHIFT 0 -#define SURFACE3_LOWER_BOUND 0x00000B34 -#define SURFACE3_LOWER_BOUND__SURF_LOWER__MASK 0x0FFFFFFF -#define SURFACE3_LOWER_BOUND__SURF_LOWER__SHIFT 0 -#define SURFACE3_UPPER_BOUND 0x00000B38 -#define SURFACE3_UPPER_BOUND__SURF_UPPER__MASK 0x0FFFFFFF -#define SURFACE3_UPPER_BOUND__SURF_UPPER__SHIFT 0 -#define SURFACE4_INFO 0x00000B4C -#define SURFACE4_INFO__SURF4_PITCHSEL__MASK 0x000003FF -#define SURFACE4_INFO__SURF4_PITCHSEL__SHIFT 0 -#define SURFACE4_INFO__SURF4_TILE_MODE__MASK 0x00030000 -#define SURFACE4_INFO__SURF4_TILE_MODE__SHIFT 16 -#define SURFACE4_INFO__SURF4_AP0_SWP__MASK 0x00300000 -#define SURFACE4_INFO__SURF4_AP0_SWP__SHIFT 20 -#define SURFACE4_INFO__SURF4_AP1_SWP__MASK 0x00C00000 -#define SURFACE4_INFO__SURF4_AP1_SWP__SHIFT 22 -#define SURFACE4_INFO__SURF4_WRITE_FLAG 0x01000000 -#define SURFACE4_INFO__SURF4_READ_FLAG 0x02000000 -#define SURFACE4_INFO__SURF4_TILE_MODE_R2__MASK 0x00070000 -#define SURFACE4_INFO__SURF4_TILE_MODE_R2__SHIFT 16 -#define SURFACE4_INFO__SURF4_PITCHSEL_R3__MASK 0x00001FFF -#define SURFACE4_INFO__SURF4_PITCHSEL_R3__SHIFT 0 -#define SURFACE4_LOWER_BOUND 0x00000B44 -#define SURFACE4_LOWER_BOUND__SURF_LOWER__MASK 0x0FFFFFFF -#define SURFACE4_LOWER_BOUND__SURF_LOWER__SHIFT 0 -#define SURFACE4_UPPER_BOUND 0x00000B48 -#define SURFACE4_UPPER_BOUND__SURF_UPPER__MASK 0x0FFFFFFF -#define SURFACE4_UPPER_BOUND__SURF_UPPER__SHIFT 0 -#define SURFACE5_INFO 0x00000B5C -#define SURFACE5_INFO__SURF5_PITCHSEL__MASK 0x000003FF -#define SURFACE5_INFO__SURF5_PITCHSEL__SHIFT 0 -#define SURFACE5_INFO__SURF5_TILE_MODE__MASK 0x00030000 -#define SURFACE5_INFO__SURF5_TILE_MODE__SHIFT 16 -#define SURFACE5_INFO__SURF5_AP0_SWP__MASK 0x00300000 -#define SURFACE5_INFO__SURF5_AP0_SWP__SHIFT 20 -#define SURFACE5_INFO__SURF5_AP1_SWP__MASK 0x00C00000 -#define SURFACE5_INFO__SURF5_AP1_SWP__SHIFT 22 -#define SURFACE5_INFO__SURF5_WRITE_FLAG 0x01000000 -#define SURFACE5_INFO__SURF5_READ_FLAG 0x02000000 -#define SURFACE5_INFO__SURF5_TILE_MODE_R2__MASK 0x00070000 -#define SURFACE5_INFO__SURF5_TILE_MODE_R2__SHIFT 16 -#define SURFACE5_INFO__SURF5_PITCHSEL_R3__MASK 0x00001FFF -#define SURFACE5_INFO__SURF5_PITCHSEL_R3__SHIFT 0 -#define SURFACE5_LOWER_BOUND 0x00000B54 -#define SURFACE5_LOWER_BOUND__SURF_LOWER__MASK 0x0FFFFFFF -#define SURFACE5_LOWER_BOUND__SURF_LOWER__SHIFT 0 -#define SURFACE5_UPPER_BOUND 0x00000B58 -#define SURFACE5_UPPER_BOUND__SURF_UPPER__MASK 0x0FFFFFFF -#define SURFACE5_UPPER_BOUND__SURF_UPPER__SHIFT 0 -#define SURFACE6_INFO 0x00000B6C -#define SURFACE6_INFO__SURF6_PITCHSEL__MASK 0x000003FF -#define SURFACE6_INFO__SURF6_PITCHSEL__SHIFT 0 -#define SURFACE6_INFO__SURF6_TILE_MODE__MASK 0x00030000 -#define SURFACE6_INFO__SURF6_TILE_MODE__SHIFT 16 -#define SURFACE6_INFO__SURF6_AP0_SWP__MASK 0x00300000 -#define SURFACE6_INFO__SURF6_AP0_SWP__SHIFT 20 -#define SURFACE6_INFO__SURF6_AP1_SWP__MASK 0x00C00000 -#define SURFACE6_INFO__SURF6_AP1_SWP__SHIFT 22 -#define SURFACE6_INFO__SURF6_WRITE_FLAG 0x01000000 -#define SURFACE6_INFO__SURF6_READ_FLAG 0x02000000 -#define SURFACE6_INFO__SURF6_TILE_MODE_R2__MASK 0x00070000 -#define SURFACE6_INFO__SURF6_TILE_MODE_R2__SHIFT 16 -#define SURFACE6_INFO__SURF6_PITCHSEL_R3__MASK 0x00001FFF -#define SURFACE6_INFO__SURF6_PITCHSEL_R3__SHIFT 0 -#define SURFACE6_LOWER_BOUND 0x00000B64 -#define SURFACE6_LOWER_BOUND__SURF_LOWER__MASK 0x0FFFFFFF -#define SURFACE6_LOWER_BOUND__SURF_LOWER__SHIFT 0 -#define SURFACE6_UPPER_BOUND 0x00000B68 -#define SURFACE6_UPPER_BOUND__SURF_UPPER__MASK 0x0FFFFFFF -#define SURFACE6_UPPER_BOUND__SURF_UPPER__SHIFT 0 -#define SURFACE7_INFO 0x00000B7C -#define SURFACE7_INFO__SURF7_PITCHSEL__MASK 0x000003FF -#define SURFACE7_INFO__SURF7_PITCHSEL__SHIFT 0 -#define SURFACE7_INFO__SURF7_TILE_MODE__MASK 0x00030000 -#define SURFACE7_INFO__SURF7_TILE_MODE__SHIFT 16 -#define SURFACE7_INFO__SURF7_AP0_SWP__MASK 0x00300000 -#define SURFACE7_INFO__SURF7_AP0_SWP__SHIFT 20 -#define SURFACE7_INFO__SURF7_AP1_SWP__MASK 0x00C00000 -#define SURFACE7_INFO__SURF7_AP1_SWP__SHIFT 22 -#define SURFACE7_INFO__SURF7_WRITE_FLAG 0x01000000 -#define SURFACE7_INFO__SURF7_READ_FLAG 0x02000000 -#define SURFACE7_INFO__SURF7_TILE_MODE_R2__MASK 0x00070000 -#define SURFACE7_INFO__SURF7_TILE_MODE_R2__SHIFT 16 -#define SURFACE7_INFO__SURF7_PITCHSEL_R3__MASK 0x00001FFF -#define SURFACE7_INFO__SURF7_PITCHSEL_R3__SHIFT 0 -#define SURFACE7_LOWER_BOUND 0x00000B74 -#define SURFACE7_LOWER_BOUND__SURF_LOWER__MASK 0x0FFFFFFF -#define SURFACE7_LOWER_BOUND__SURF_LOWER__SHIFT 0 -#define SURFACE7_UPPER_BOUND 0x00000B78 -#define SURFACE7_UPPER_BOUND__SURF_UPPER__MASK 0x0FFFFFFF -#define SURFACE7_UPPER_BOUND__SURF_UPPER__SHIFT 0 -#define ISYNC_CNTL 0x00001724 -#define ISYNC_CNTL__ISYNC_ANY2D_IDLE3D 0x00000001 -#define ISYNC_CNTL__ISYNC_ANY3D_IDLE2D 0x00000002 -#define ISYNC_CNTL__ISYNC_TRIG2D_IDLE3D 0x00000004 -#define ISYNC_CNTL__ISYNC_TRIG3D_IDLE2D 0x00000008 -#define ISYNC_CNTL__ISYNC_WAIT_IDLEGUI 0x00000010 -#define ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI 0x00000020 -#define GA_SOFT_RESET 0x0000429C -#define GA_SOFT_RESET__SOFT_RESET_COUNT__MASK 0x0000FFFF -#define GA_SOFT_RESET__SOFT_RESET_COUNT__SHIFT 0 -#define RBBM_CNTL 0x000000EC -#define RBBM_CNTL__RB_SETTLE__MASK 0x0000000F -#define RBBM_CNTL__RB_SETTLE__SHIFT 0 -#define RBBM_CNTL__ABORTCLKS_HI__MASK 0x00000070 -#define RBBM_CNTL__ABORTCLKS_HI__SHIFT 4 -#define RBBM_CNTL__ABORTCLKS_CP__MASK 0x00000700 -#define RBBM_CNTL__ABORTCLKS_CP__SHIFT 8 -#define RBBM_CNTL__ABORTCLKS_CFIFO__MASK 0x00007000 -#define RBBM_CNTL__ABORTCLKS_CFIFO__SHIFT 12 -#define RBBM_CNTL__CPQ_DATA_SWAP 0x00020000 -#define RBBM_CNTL__NO_ABORT_IDCT 0x00200000 -#define RBBM_CNTL__NO_ABORT_BIOS 0x00400000 -#define RBBM_CNTL__NO_ABORT_FB 0x00800000 -#define RBBM_CNTL__NO_ABORT_CP 0x01000000 -#define RBBM_CNTL__NO_ABORT_HI 0x02000000 -#define RBBM_CNTL__NO_ABORT_HDP 0x04000000 -#define RBBM_CNTL__NO_ABORT_MC 0x08000000 -#define RBBM_CNTL__NO_ABORT_AIC 0x10000000 -#define RBBM_CNTL__NO_ABORT_VIP 0x20000000 -#define RBBM_CNTL__NO_ABORT_DISP 0x40000000 -#define RBBM_CNTL__NO_ABORT_CG 0x80000000 -#define RBBM_CNTL__NO_ABORT_VAP 0x00080000 -#define RBBM_CNTL__NO_ABORT_GA 0x00100000 -#define RBBM_CNTL__NO_ABORT_TVOUT 0x00800000 -#define RBBM_STATUS 0x00000E40 -#define RBBM_STATUS__CMDFIFO_AVAIL__MASK 0x0000007F -#define RBBM_STATUS__CMDFIFO_AVAIL__SHIFT 0 -#define RBBM_STATUS__HIRQ_ON_RBB 0x00000100 -#define RBBM_STATUS__CPRQ_ON_RBB 0x00000200 -#define RBBM_STATUS__CFRQ_ON_RBB 0x00000400 -#define RBBM_STATUS__HIRQ_IN_RTBUF 0x00000800 -#define RBBM_STATUS__CPRQ_IN_RTBUF 0x00001000 -#define RBBM_STATUS__CFRQ_IN_RTBUF 0x00002000 -#define RBBM_STATUS__CF_PIPE_BUSY 0x00004000 -#define RBBM_STATUS__ENG_EV_BUSY 0x00008000 -#define RBBM_STATUS__CP_CMDSTRM_BUSY 0x00010000 -#define RBBM_STATUS__E2_BUSY 0x00020000 -#define RBBM_STATUS__RB2D_BUSY 0x00040000 -#define RBBM_STATUS__RB3D_BUSY 0x00080000 -#define RBBM_STATUS__SE_BUSY 0x00100000 -#define RBBM_STATUS__RE_BUSY 0x00200000 -#define RBBM_STATUS__TAM_BUSY 0x00400000 -#define RBBM_STATUS__TDM_BUSY 0x00800000 -#define RBBM_STATUS__PB_BUSY 0x01000000 -#define RBBM_STATUS__GUI_ACTIVE 0x80000000 -#define RBBM_STATUS__VAP_BUSY 0x00100000 -#define RBBM_STATUS__TIM_BUSY 0x02000000 -#define RBBM_STATUS__GA_BUSY 0x04000000 -#define RBBM_STATUS__CBA2D_BUSY 0x08000000 -#define RBBM_SOFT_RESET 0x000000F0 -#define RBBM_SOFT_RESET__SOFT_RESET_CP 0x00000001 -#define RBBM_SOFT_RESET__SOFT_RESET_HI 0x00000002 -#define RBBM_SOFT_RESET__SOFT_RESET_SE 0x00000004 -#define RBBM_SOFT_RESET__SOFT_RESET_RE 0x00000008 -#define RBBM_SOFT_RESET__SOFT_RESET_PP 0x00000010 -#define RBBM_SOFT_RESET__SOFT_RESET_E2 0x00000020 -#define RBBM_SOFT_RESET__SOFT_RESET_RB 0x00000040 -#define RBBM_SOFT_RESET__SOFT_RESET_HDP 0x00000080 -#define RBBM_SOFT_RESET__SOFT_RESET_MC 0x00000100 -#define RBBM_SOFT_RESET__SOFT_RESET_AIC 0x00000200 -#define RBBM_SOFT_RESET__SOFT_RESET_VIP 0x00000400 -#define RBBM_SOFT_RESET__SOFT_RESET_DISP 0x00000800 -#define RBBM_SOFT_RESET__SOFT_RESET_CG 0x00001000 -#define RBBM_SOFT_RESET__SOFT_RESET_VAP 0x00000004 -#define RBBM_SOFT_RESET__SOFT_RESET_GA 0x00002000 -#define RBBM_SOFT_RESET__SOFT_RESET_IDCT 0x00004000 -#define RBBM_CMDFIFO_ADDR 0x00000E70 -#define RBBM_CMDFIFO_ADDR__CMDFIFO_ADDR__MASK 0x0000003F -#define RBBM_CMDFIFO_ADDR__CMDFIFO_ADDR__SHIFT 0 -#define RBBM_CMDFIFO_ADDR__CMDFIFO_ADDR_R3__MASK 0x000001FF -#define RBBM_CMDFIFO_ADDR__CMDFIFO_ADDR_R3__SHIFT 0 -#define RBBM_CMDFIFO_DATA 0x00000E74 -#define RBBM_CMDFIFO_DATA__CMDFIFO_DATA__MASK 0xFFFFFFFF -#define RBBM_CMDFIFO_DATA__CMDFIFO_DATA__SHIFT 0 -#define RBBM_CMDFIFO_STAT 0x00000E7C -#define RBBM_CMDFIFO_STAT__CMDFIFO_RPTR__MASK 0x0000003F -#define RBBM_CMDFIFO_STAT__CMDFIFO_RPTR__SHIFT 0 -#define RBBM_CMDFIFO_STAT__CMDFIFO_WPTR__MASK 0x00003F00 -#define RBBM_CMDFIFO_STAT__CMDFIFO_WPTR__SHIFT 8 -#define WAIT_UNTIL 0x00001720 -#define WAIT_UNTIL__WAIT_CRTC_PFLIP 0x00000001 -#define WAIT_UNTIL__WAIT_RE_CRTC_VLINE 0x00000002 -#define WAIT_UNTIL__WAIT_FE_CRTC_VLINE 0x00000004 -#define WAIT_UNTIL__WAIT_CRTC_VLINE 0x00000008 -#define WAIT_UNTIL__WAIT_DMA_VIPH0_IDLE 0x00000010 -#define WAIT_UNTIL__WAIT_DMA_VIPH1_IDLE 0x00000020 -#define WAIT_UNTIL__WAIT_DMA_VIPH2_IDLE 0x00000040 -#define WAIT_UNTIL__WAIT_DMA_VIPH3_IDLE 0x00000080 -#define WAIT_UNTIL__WAIT_DMA_VID_IDLE 0x00000100 -#define WAIT_UNTIL__WAIT_DMA_GUI_IDLE 0x00000200 -#define WAIT_UNTIL__WAIT_CMDFIFO 0x00000400 -#define WAIT_UNTIL__WAIT_OV0_FLIP 0x00000800 -#define WAIT_UNTIL__WAIT_OV0_SLICEDONE 0x00001000 -#define WAIT_UNTIL__WAIT_2D_IDLE 0x00004000 -#define WAIT_UNTIL__WAIT_3D_IDLE 0x00008000 -#define WAIT_UNTIL__WAIT_2D_IDLECLEAN 0x00010000 -#define WAIT_UNTIL__WAIT_3D_IDLECLEAN 0x00020000 -#define WAIT_UNTIL__WAIT_HOST_IDLECLEAN 0x00040000 -#define WAIT_UNTIL__WAIT_EXTERN_SIG 0x00080000 -#define WAIT_UNTIL__CMDFIFO_ENTRIES__MASK 0x07F00000 -#define WAIT_UNTIL__CMDFIFO_ENTRIES__SHIFT 20 -#define WAIT_UNTIL__WAIT_BOTH_CRTC_PFLIP 0x40000000 -#define WAIT_UNTIL__ENG_DISPLAY_SELECT 0x80000000 -#define WAIT_UNTIL__WAIT_AGP_FLUSH 0x00002000 -#define WAIT_UNTIL__WAIT_IDCT_SEMAPHORE 0x08000000 -#define WAIT_UNTIL__WAIT_VAP_IDLE 0x10000000 -#define DISPLAY_BASE_ADDR 0x0000023C -#define DISPLAY_BASE_ADDR__DISPLAY_BASE_ADDR__MASK 0xFFFFFFFF -#define DISPLAY_BASE_ADDR__DISPLAY_BASE_ADDR__SHIFT 0 -#define CRTC2_DISPLAY_BASE_ADDR 0x0000033C -#define CRTC2_DISPLAY_BASE_ADDR__CRTC2_DISPLAY_BASE_ADDR__MASK 0xFFFFFFFF -#define CRTC2_DISPLAY_BASE_ADDR__CRTC2_DISPLAY_BASE_ADDR__SHIFT 0 -#define AIC_CTRL 0x000001D0 -#define AIC_CTRL__TRANSLATE_EN 0x00000001 -#define AIC_CTRL__HW_0_DEBUG 0x00000002 -#define AIC_CTRL__HW_1_DEBUG 0x00000004 -#define AIC_CTRL__HW_2_DEBUG 0x00000008 -#define AIC_CTRL__HW_3_DEBUG 0x00000010 -#define AIC_CTRL__HW_4_DEBUG 0x00000020 -#define AIC_CTRL__HW_5_DEBUG 0x00000040 -#define AIC_CTRL__HW_6_DEBUG 0x00000080 -#define AIC_CTRL__HW_7_DEBUG 0x00000100 -#define AIC_CTRL__HW_8_DEBUG 0x00000200 -#define AIC_CTRL__HW_9_DEBUG 0x00000400 -#define AIC_CTRL__HW_A_DEBUG 0x00000800 -#define AIC_CTRL__HW_B_DEBUG 0x00001000 -#define AIC_CTRL__HW_C_DEBUG 0x00002000 -#define AIC_CTRL__HW_D_DEBUG 0x00004000 -#define AIC_CTRL__HW_E_DEBUG 0x00008000 -#define AIC_CTRL__HW_F_DEBUG 0x00010000 -#define AIC_CTRL__HW_10_DEBUG 0x00020000 -#define AIC_CTRL__HW_11_DEBUG 0x00040000 -#define AIC_CTRL__HW_12_DEBUG 0x00080000 -#define AIC_CTRL__HW_13_DEBUG 0x00100000 -#define AIC_CTRL__HW_14_DEBUG 0x00200000 -#define AIC_CTRL__HW_15_DEBUG 0x00400000 -#define AIC_CTRL__HW_16_DEBUG 0x00800000 -#define AIC_CTRL__HW_17_DEBUG 0x01000000 -#define AIC_CTRL__HW_18_DEBUG 0x02000000 -#define AIC_CTRL__HW_19_DEBUG 0x04000000 -#define AIC_CTRL__HW_1A_DEBUG 0x08000000 -#define AIC_CTRL__HW_1B_DEBUG 0x10000000 -#define AIC_CTRL__HW_1C_DEBUG 0x20000000 -#define AIC_CTRL__HW_1D_DEBUG 0x40000000 -#define AIC_CTRL__HW_1E_DEBUG 0x80000000 -#define AIC_CTRL__DIS_OUT_OF_PCI_GART_ACCESS 0x00000002 -#define AIC_CTRL__HW_02_DEBUG 0x00000004 -#define AIC_CTRL__HW_03_DEBUG 0x00000008 -#define AIC_CTRL__TEST_RBF_DIV_VAL__MASK 0x00000070 -#define AIC_CTRL__TEST_RBF_DIV_VAL__SHIFT 4 -#define AIC_CTRL__TEST_RBF_EN 0x00000080 -#define AIC_CTRL__HW_08_DEBUG 0x00000100 -#define AIC_CTRL__HW_09_DEBUG 0x00000200 -#define AIC_CTRL__HW_10_DEBUG_R3 0x00000400 -#define AIC_CTRL__HW_11_DEBUG_R3 0x00000800 -#define AIC_CTRL__HW_12_DEBUG_R3 0x00001000 -#define AIC_CTRL__HW_13_DEBUG_R3 0x00002000 -#define AIC_CTRL__HW_14_DEBUG_R3 0x00004000 -#define AIC_CTRL__HW_15_DEBUG_R3 0x00008000 -#define AIC_CTRL__HW_16_DEBUG_R3 0x00010000 -#define AIC_CTRL__HW_17_DEBUG_R3 0x00020000 -#define AIC_CTRL__HW_18_DEBUG_R3 0x00040000 -#define AIC_CTRL__HW_19_DEBUG_R3 0x00080000 -#define AIC_CTRL__HW_20_DEBUG 0x00100000 -#define AIC_CTRL__HW_21_DEBUG 0x00200000 -#define AIC_CTRL__HW_22_DEBUG 0x00400000 -#define AIC_CTRL__HW_23_DEBUG 0x00800000 -#define AIC_CTRL__HW_24_DEBUG 0x01000000 -#define AIC_CTRL__HW_25_DEBUG 0x02000000 -#define AIC_CTRL__HW_26_DEBUG 0x04000000 -#define AIC_CTRL__HW_27_DEBUG 0x08000000 -#define AIC_CTRL__HW_28_DEBUG 0x10000000 -#define AIC_CTRL__HW_29_DEBUG 0x20000000 -#define AIC_CTRL__HW_30_DEBUG 0x40000000 -#define AIC_CTRL__HW_31_DEBUG 0x80000000 -#define BUS_CNTL 0x00000030 -#define BUS_CNTL__BUS_DBL_RESYNC 0x00000001 -#define BUS_CNTL__BUS_MSTR_RESET 0x00000002 -#define BUS_CNTL__BUS_FLUSH_BUF 0x00000004 -#define BUS_CNTL__BUS_STOP_REQ_DIS 0x00000008 -#define BUS_CNTL__BUS_READ_COMBINE_EN 0x00000010 -#define BUS_CNTL__BUS_WRT_COMBINE_EN 0x00000020 -#define BUS_CNTL__BUS_MASTER_DIS 0x00000040 -#define BUS_CNTL__BIOS_ROM_WRT_EN 0x00000080 -#define BUS_CNTL__BUS_PREFETCH_MODE__MASK 0x00000300 -#define BUS_CNTL__BUS_PREFETCH_MODE__SHIFT 8 -#define BUS_CNTL__BUS_VGA_PREFETCH_EN 0x00000400 -#define BUS_CNTL__BUS_SGL_READ_DISABLE 0x00000800 -#define BUS_CNTL__BIOS_DIS_ROM 0x00001000 -#define BUS_CNTL__BUS_PCI_READ_RETRY_EN 0x00002000 -#define BUS_CNTL__BUS_AGP_AD_STEPPING_EN 0x00004000 -#define BUS_CNTL__BUS_PCI_WRT_RETRY_EN 0x00008000 -#define BUS_CNTL__BUS_RETRY_WS__MASK 0x000F0000 -#define BUS_CNTL__BUS_RETRY_WS__SHIFT 16 -#define BUS_CNTL__BUS_MSTR_RD_MULT 0x00100000 -#define BUS_CNTL__BUS_MSTR_RD_LINE 0x00200000 -#define BUS_CNTL__BUS_SUSPEND 0x00400000 -#define BUS_CNTL__LAT_16X 0x00800000 -#define BUS_CNTL__BUS_RD_DISCARD_EN 0x01000000 -#define BUS_CNTL__ENFRCWRDY 0x02000000 -#define BUS_CNTL__BUS_MSTR_WS 0x04000000 -#define BUS_CNTL__BUS_PARKING_DIS 0x08000000 -#define BUS_CNTL__BUS_MSTR_DISCONNECT_EN 0x10000000 -#define BUS_CNTL__SERR_EN 0x20000000 -#define BUS_CNTL__BUS_READ_BURST 0x40000000 -#define BUS_CNTL__BUS_RDY_READ_DLY 0x80000000 -#define BUS_CNTL__BUS_PM4_READ_COMBINE_EN 0x00000010 -#define BUS_CNTL__BM_DAC_CRIPPLE 0x00000100 -#define BUS_CNTL__BUS_NON_PM4_READ_COMBINE_EN 0x00000200 -#define BUS_CNTL__BUS_XFERD_DISCARD_EN 0x00000400 -#define MC_STATUS 0x00000150 -#define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001 -#define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002 -#define MC_STATUS__MC_IDLE 0x00000004 -#define MC_STATUS__SPARE__MASK 0x0000FFF8 -#define MC_STATUS__SPARE__SHIFT 3 -#define MC_STATUS__IMP_N_VALUE_R_BACK__MASK 0x00000078 -#define MC_STATUS__IMP_N_VALUE_R_BACK__SHIFT 3 -#define MC_STATUS__IMP_P_VALUE_R_BACK__MASK 0x00000780 -#define MC_STATUS__IMP_P_VALUE_R_BACK__SHIFT 7 -#define MC_STATUS__TEST_OUT_R_BACK 0x00000800 -#define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000 -#define MC_STATUS__IMP_N_VALUE_A_R_BACK__MASK 0x0001E000 -#define MC_STATUS__IMP_N_VALUE_A_R_BACK__SHIFT 13 -#define MC_STATUS__IMP_P_VALUE_A_R_BACK__MASK 0x001E0000 -#define MC_STATUS__IMP_P_VALUE_A_R_BACK__SHIFT 17 -#define MC_STATUS__IMP_N_VALUE_CK_R_BACK__MASK 0x01E00000 -#define MC_STATUS__IMP_N_VALUE_CK_R_BACK__SHIFT 21 -#define MC_STATUS__IMP_P_VALUE_CK_R_BACK__MASK 0x1E000000 -#define MC_STATUS__IMP_P_VALUE_CK_R_BACK__SHIFT 25 -#define MC_STATUS__MEM_PWRUP_COMPL_C 0x00000004 -#define MC_STATUS__MEM_PWRUP_COMPL_D 0x00000008 -#define MC_STATUS__MC_IDLE_R3 0x00000010 -#define MC_STATUS__IMP_CAL_COUNT__MASK 0x0000F000 -#define MC_STATUS__IMP_CAL_COUNT__SHIFT 12 -#define OV0_SCALE_CNTL 0x00000420 -#define OV0_SCALE_CNTL__OV0_NO_READ_BEHIND_SCAN 0x00000002 -#define OV0_SCALE_CNTL__OV0_HORZ_PICK_NEAREST 0x00000004 -#define OV0_SCALE_CNTL__OV0_VERT_PICK_NEAREST 0x00000008 -#define OV0_SCALE_CNTL__OV0_SIGNED_UV 0x00000010 -#define OV0_SCALE_CNTL__OV0_GAMMA_SEL__MASK 0x000000E0 -#define OV0_SCALE_CNTL__OV0_GAMMA_SEL__SHIFT 5 -#define OV0_SCALE_CNTL__OV0_SURFACE_FORMAT__MASK 0x00000F00 -#define OV0_SCALE_CNTL__OV0_SURFACE_FORMAT__SHIFT 8 -#define OV0_SURFACE_FORMAT__RESERVED0 0x0 -#define OV0_SURFACE_FORMAT__RESERVED1 0x100 -#define OV0_SURFACE_FORMAT__RESERVED2 0x200 -#define OV0_SURFACE_FORMAT__16BPP_ARGB 0x300 -#define OV0_SURFACE_FORMAT__16BPP_RGB 0x400 -#define OV0_SURFACE_FORMAT__RESERVED5 0x500 -#define OV0_SURFACE_FORMAT__32BPP_ARGB 0x600 -#define OV0_SURFACE_FORMAT__RESERVED7 0x700 -#define OV0_SURFACE_FORMAT__RESERVED8 0x800 -#define OV0_SURFACE_FORMAT__IF09_PLANAR 0x900 -#define OV0_SURFACE_FORMAT__YV12_PLANAR 0xA00 -#define OV0_SURFACE_FORMAT__YUY2_PACKED 0xB00 -#define OV0_SURFACE_FORMAT__UYVY_PACKED 0xC00 -#define OV0_SURFACE_FORMAT__YYUV9_PLANAR 0xD00 -#define OV0_SURFACE_FORMAT__YYUV12_PLANAR 0xE00 -#define OV0_SURFACE_FORMAT__RESERVED15 0xF00 -#define OV0_SCALE_CNTL__OV0_ADAPTIVE_DEINT 0x00001000 -#define OV0_SCALE_CNTL__OV0_CRTC_SEL 0x00004000 -#define OV0_SCALE_CNTL__OV0_BURST_PER_PLANE__MASK 0x007F0000 -#define OV0_SCALE_CNTL__OV0_BURST_PER_PLANE__SHIFT 16 -#define OV0_SCALE_CNTL__OV0_DOUBLE_BUFFER_REGS 0x01000000 -#define OV0_SCALE_CNTL__OV0_BANDWIDTH 0x04000000 -#define OV0_SCALE_CNTL__OV0_LIN_TRANS_BYPASS 0x10000000 -#define OV0_SCALE_CNTL__OV0_INT_EMU 0x20000000 -#define OV0_SCALE_CNTL__OV0_OVERLAY_EN__MASK 0x40000000 -#define OV0_SCALE_CNTL__OV0_OVERLAY_EN__SHIFT 30 -#define OV0_OVERLAY_EN__ENABLE 0x40000000 -#define OV0_SCALE_CNTL__OV0_SOFT_RESET__MASK 0x80000000 -#define OV0_SCALE_CNTL__OV0_SOFT_RESET__SHIFT 31 -#define OV0_SOFT_RESET__RESET 0x80000000 -#define OV0_SCALE_CNTL__OV0_TEMPORAL_DEINT 0x00002000 -#define OV0_SCALE_CNTL__OV0_PULLDOWN_ON_P1_ONLY 0x00008000 -#define OV0_SCALE_CNTL__OV0_FULL_BYPASS 0x00000020 -#define OV0_SCALE_CNTL__OV0_DYNAMIC_EXT 0x00000040 -#define OV0_SCALE_CNTL__OV0_RGB30_ON 0x00000080 -#define CRTC2_GEN_CNTL 0x000003F8 -#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001 -#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002 -#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010 -#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020 -#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040 -#define CRTC2_GEN_CNTL__CRT2_ON 0x00000080 -#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH__MASK 0x00000F00 -#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH__SHIFT 8 -#define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000 -#define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000 -#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE__MASK 0x00700000 -#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE__SHIFT 20 -#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000 -#define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000 -#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000 -#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000 -#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000 -#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000 -#define CRTC2_GEN_CNTL__CRTC2_MODE9_COLOR_ORDER 0x00001000 -#define CRTC2_GEN_CNTL__CRTC2_FIX_VSYNC_EDGE_POSITION_EN 0x40000000 -#define CRTC2_OFFSET 0x00000324 -#define CRTC2_OFFSET__CRTC2_OFFSET__MASK 0x07FFFFFF -#define CRTC2_OFFSET__CRTC2_OFFSET__SHIFT 0 -#define CRTC2_OFFSET__CRTC2_GUI_TRIG_OFFSET 0x40000000 -#define CRTC2_OFFSET__CRTC2_OFFSET_LOCK 0x80000000 -#define CRTC2_OFFSET__CRTC2_OFFSET_R3__MASK 0x0FFFFFFF -#define CRTC2_OFFSET__CRTC2_OFFSET_R3__SHIFT 0 -#define CRTC2_OFFSET_CNTL 0x00000328 -#define CRTC2_OFFSET_CNTL__CRTC2_TILE_LINE__MASK 0x0000000F -#define CRTC2_OFFSET_CNTL__CRTC2_TILE_LINE__SHIFT 0 -#define CRTC2_OFFSET_CNTL__CRTC2_TILE_EN 0x00008000 -#define CRTC2_OFFSET_CNTL__CRTC2_OFFSET_FLIP_CNTL 0x00010000 -#define CRTC2_OFFSET_CNTL__CRTC2_GUI_TRIG_OFFSET_LEFT_EN 0x10000000 -#define CRTC2_OFFSET_CNTL__CRTC2_GUI_TRIG_OFFSET 0x40000000 -#define CRTC2_OFFSET_CNTL__CRTC2_OFFSET_LOCK 0x80000000 -#define CRTC2_OFFSET_CNTL__CRTC2_TILE_LINE_RIGHT__MASK 0x000000F0 -#define CRTC2_OFFSET_CNTL__CRTC2_TILE_LINE_RIGHT__SHIFT 4 -#define CRTC2_OFFSET_CNTL__CRTC2_TILE_EN_RIGHT 0x00004000 -#define CRTC2_OFFSET_CNTL__CRTC2_STEREO_OFFSET_EN 0x00020000 -#define CRTC2_OFFSET_CNTL__CRTC2_STEREO_SYNC_EN__MASK 0x000C0000 -#define CRTC2_OFFSET_CNTL__CRTC2_STEREO_SYNC_EN__SHIFT 18 -#define CRTC2_OFFSET_CNTL__CRTC2_STEREO_SYNC 0x00200000 -#define CRTC2_OFFSET_CNTL__CRTC2_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000 -#define CRTC2_OFFSET_CNTL__CRTC2_X_Y_MODE_EN_RIGHT 0x00000100 -#define CRTC2_OFFSET_CNTL__CRTC2_X_Y_MODE_EN 0x00000200 -#define CRTC2_OFFSET_CNTL__CRTC2_MICRO_TILE_EN_RIGHT 0x00001000 -#define CRTC2_OFFSET_CNTL__CRTC2_MICRO_TILE_EN 0x00002000 -#define CRTC2_OFFSET_CNTL__CRTC2_MACRO_TILE_EN_RIGHT 0x00004000 -#define CRTC2_OFFSET_CNTL__CRTC2_MACRO_TILE_EN 0x00008000 -#define CUR_OFFSET 0x00000260 -#define CUR_OFFSET__CUR_OFFSET__MASK 0x07FFFFFF -#define CUR_OFFSET__CUR_OFFSET__SHIFT 0 -#define CUR_OFFSET__CUR_LOCK 0x80000000 -#define CUR2_OFFSET 0x00000360 -#define CUR2_OFFSET__CUR2_OFFSET__MASK 0x07FFFFFF -#define CUR2_OFFSET__CUR2_OFFSET__SHIFT 0 -#define CUR2_OFFSET__CUR2_LOCK 0x80000000 -#define HOST_PATH_CNTL 0x00000130 -#define HOST_PATH_CNTL__HDP_APER_CNTL 0x00800000 -#define HOST_PATH_CNTL__HP_LIN_RD_CACHE_DIS 0x01000000 -#define HOST_PATH_CNTL__HP_RBBM_LOCK_DIS 0x02000000 -#define HOST_PATH_CNTL__HDP_SOFT_RESET 0x04000000 -#define HOST_PATH_CNTL__HDP_WRITE_COMBINER_TIMEOUT__MASK 0x70000000 -#define HOST_PATH_CNTL__HDP_WRITE_COMBINER_TIMEOUT__SHIFT 28 -#define HOST_PATH_CNTL__HP_TEST_RST_CNTL 0x80000000 -#define HOST_PATH_CNTL__HDP_WRITE_THROUGH_CACHE_DIS 0x00400000 -#define HOST_PATH_CNTL__HDP_READ_BUFFER_INVALIDATE 0x08000000 -#define DST_PITCH_OFFSET 0x0000142C -#define DST_PITCH_OFFSET__DST_OFFSET__MASK 0x003FFFFF -#define DST_PITCH_OFFSET__DST_OFFSET__SHIFT 0 -#define DST_PITCH_OFFSET__DST_PITCH__MASK 0x3FC00000 -#define DST_PITCH_OFFSET__DST_PITCH__SHIFT 22 -#define DST_PITCH_OFFSET__DST_TILE__MASK 0xC0000000 -#define DST_PITCH_OFFSET__DST_TILE__SHIFT 30 -#define DST_TILE__MACRO 0x1 -#define DST_TILE__MICRO 0x2 -#define SRC_PITCH_OFFSET 0x00001428 -#define SRC_PITCH_OFFSET__SRC_OFFSET__MASK 0x003FFFFF -#define SRC_PITCH_OFFSET__SRC_OFFSET__SHIFT 0 -#define SRC_PITCH_OFFSET__SRC_PITCH__MASK 0x3FC00000 -#define SRC_PITCH_OFFSET__SRC_PITCH__SHIFT 22 -#define SRC_PITCH_OFFSET__SRC_TILE 0x40000000 -#define DEFAULT_SC_BOTTOM_RIGHT 0x000016E8 -#define DEFAULT_SC_BOTTOM_RIGHT__DEFAULT_SC_RIGHT__MASK 0x00003FFF -#define DEFAULT_SC_BOTTOM_RIGHT__DEFAULT_SC_RIGHT__SHIFT 0 -#define DEFAULT_SC_BOTTOM_RIGHT__DEFAULT_SC_BOTTOM__MASK 0x3FFF0000 -#define DEFAULT_SC_BOTTOM_RIGHT__DEFAULT_SC_BOTTOM__SHIFT 16 -#define DEFAULT2_SC_BOTTOM_RIGHT 0x000016DC -#define DEFAULT2_SC_BOTTOM_RIGHT__DEFAULT_SC_RIGHT__MASK 0x00003FFF -#define DEFAULT2_SC_BOTTOM_RIGHT__DEFAULT_SC_RIGHT__SHIFT 0 -#define DEFAULT2_SC_BOTTOM_RIGHT__DEFAULT_SC_BOTTOM__MASK 0x3FFF0000 -#define DEFAULT2_SC_BOTTOM_RIGHT__DEFAULT_SC_BOTTOM__SHIFT 16 -#define DP_DATATYPE 0x000016C4 -#define DP_DATATYPE__DP_DST_DATATYPE__MASK 0x0000000F -#define DP_DATATYPE__DP_DST_DATATYPE__SHIFT 0 -#define DP_DATATYPE__DP_BRUSH_DATATYPE__MASK 0x00000F00 -#define DP_DATATYPE__DP_BRUSH_DATATYPE__SHIFT 8 -#define DP_DATATYPE__DP_SRC_DATATYPE__MASK 0x00070000 -#define DP_DATATYPE__DP_SRC_DATATYPE__SHIFT 16 -#define DP_DATATYPE__DP_BYTE_PIX_ORDER 0x40000000 -#define DP_GUI_MASTER_CNTL 0x0000146C -#define DP_GUI_MASTER_CNTL__GMC_SRC_PITCH_OFFSET_CNTL 0x00000001 -#define DP_GUI_MASTER_CNTL__GMC_DST_PITCH_OFFSET_CNTL 0x00000002 -#define DP_GUI_MASTER_CNTL__GMC_SRC_CLIPPING 0x00000004 -#define DP_GUI_MASTER_CNTL__GMC_DST_CLIPPING 0x00000008 -#define DP_GUI_MASTER_CNTL__GMC_BRUSH_DATATYPE__MASK 0x000000F0 -#define DP_GUI_MASTER_CNTL__GMC_BRUSH_DATATYPE__SHIFT 4 -#define GMC_BRUSH_DATATYPE__8X8_MONO_FG_BG 0x0 -#define GMC_BRUSH_DATATYPE__8X8_MONO_FG 0x1 -#define GMC_BRUSH_DATATYPE__32X1_MONO_LINE_FG_BG 0x6 -#define GMC_BRUSH_DATATYPE__32X1_MONO_LINE_FG 0x7 -#define GMC_BRUSH_DATATYPE__8X8_COLOR 0xA -#define GMC_BRUSH_DATATYPE__SOLID_COLOR_FG 0xD -#define GMC_BRUSH_DATATYPE__SOLID_COLOR_RESERVED 0xF -#define GMC_BRUSH_DATATYPE__SOLID 0xD0 -#define GMC_BRUSH_DATATYPE__MONO8x8 0x0 -#define GMC_BRUSH_DATATYPE__COLOR8x8 0xA0 -#define DP_GUI_MASTER_CNTL__GMC_DST_DATATYPE__MASK 0x00000F00 -#define DP_GUI_MASTER_CNTL__GMC_DST_DATATYPE__SHIFT 8 -#define GMC_DST_DATATYPE__8BPP_CLUT 0x2 -#define GMC_DST_DATATYPE__16BPP_1555 0x3 -#define GMC_DST_DATATYPE__16BPP_565 0x4 -#define GMC_DST_DATATYPE__32BPP_8888 0x6 -#define GMC_DST_DATATYPE__CI8 0x200 -#define GMC_DST_DATATYPE__RGB16_1555 0x300 -#define GMC_DST_DATATYPE__RGB16_565 0x400 -#define GMC_DST_DATATYPE__RGB32 0x600 -#define DP_GUI_MASTER_CNTL__GMC_SRC_DATATYPE__MASK 0x00003000 -#define DP_GUI_MASTER_CNTL__GMC_SRC_DATATYPE__SHIFT 12 -#define GMC_SRC_DATATYPE__BUILD(x) 0x0 -#define GMC_SRC_DATATYPE__MONO_OPAQUE 0x0 -#define GMC_SRC_DATATYPE__MONO_TRANSPARENT 0x0 -#define GMC_SRC_DATATYPE__SAME_AS_DST 0x0 -#define GMC_SRC_DATATYPE__8BPP_CLUT_XLAT 0x0 -#define GMC_SRC_DATATYPE__32BPP_CLUT_XLAT 0x0 -#define GMC_SRC_DATATYPE__MONO_FG_BG 0x0 -#define GMC_SRC_DATATYPE__MONO_FG 0x1000 -#define GMC_SRC_DATATYPE__COLOR 0x3000 -#define GMC_SRC_DATATYPE__DST 0x3000 -#define DP_GUI_MASTER_CNTL__GMC_BYTE_PIX_ORDER 0x00004000 -#define DP_GUI_MASTER_CNTL__GMC_DEFAULT_SEL 0x00008000 -#define DP_GUI_MASTER_CNTL__GMC_ROP3__MASK 0x00FF0000 -#define DP_GUI_MASTER_CNTL__GMC_ROP3__SHIFT 16 -#define GMC_ROP3__SRCCPY 0xCC -#define GMC_ROP3__WHITENESS 0xFF -#define GMC_ROP3__BLACKNESS 0x0 -#define DP_GUI_MASTER_CNTL__GMC_DP_SRC_SOURCE__MASK 0x07000000 -#define DP_GUI_MASTER_CNTL__GMC_DP_SRC_SOURCE__SHIFT 24 -#define GMC_DP_SRC_SOURCE__VIDEO_MEM 0x2 -#define GMC_DP_SRC_SOURCE__HOSTDATA 0x3 -#define GMC_DP_SRC_SOURCE__HOSTDATA_BYTE 0x4 -#define DP_GUI_MASTER_CNTL__GMC_SRC_DATATYPE2 0x08000000 -#define DP_GUI_MASTER_CNTL__GMC_CLR_CMP_FCN_DIS 0x10000000 -#define DP_GUI_MASTER_CNTL__GMC_WR_MSK_DIS 0x40000000 -#define DP_BRUSH_FRGD_CLR 0x0000147C -#define DP_BRUSH_FRGD_CLR__DP_BRUSH_FRGD_CLR__MASK 0xFFFFFFFF -#define DP_BRUSH_FRGD_CLR__DP_BRUSH_FRGD_CLR__SHIFT 0 -#define DP_BRUSH_BKGD_CLR 0x00001478 -#define DP_BRUSH_BKGD_CLR__DP_BRUSH_BKGD_CLR__MASK 0xFFFFFFFF -#define DP_BRUSH_BKGD_CLR__DP_BRUSH_BKGD_CLR__SHIFT 0 -#define DP_SRC_FRGD_CLR 0x000015D8 -#define DP_SRC_FRGD_CLR__DP_SRC_FRGD_CLR__MASK 0xFFFFFFFF -#define DP_SRC_FRGD_CLR__DP_SRC_FRGD_CLR__SHIFT 0 -#define DP_SRC_BKGD_CLR 0x000015DC -#define DP_SRC_BKGD_CLR__DP_SRC_BKGD_CLR__MASK 0xFFFFFFFF -#define DP_SRC_BKGD_CLR__DP_SRC_BKGD_CLR__SHIFT 0 -#define DP_WRITE_MSK 0x000016CC -#define DP_WRITE_MSK__DP_WRITE_MSK__MASK 0xFFFFFFFF -#define DP_WRITE_MSK__DP_WRITE_MSK__SHIFT 0 -#define US_CONFIG 0x00004600 -#define US_CONFIG__NLEVEL__MASK 0x00000007 -#define US_CONFIG__NLEVEL__SHIFT 0 -#define US_CONFIG__FIRST_TEX 0x00000008 -#define US_CONFIG__PERF0__MASK 0x000001F0 -#define US_CONFIG__PERF0__SHIFT 4 -#define US_CONFIG__PERF1__MASK 0x00003E00 -#define US_CONFIG__PERF1__SHIFT 9 -#define US_CONFIG__PERF2__MASK 0x0007C000 -#define US_CONFIG__PERF2__SHIFT 14 -#define US_CONFIG__PERF3__MASK 0x00F80000 -#define US_CONFIG__PERF3__SHIFT 19 -#define US_RESET 0x0000460C -#define VAP_PVS_STATE_FLUSH_REG 0x00002284 -#define VAP_PVS_STATE_FLUSH_REG__DATA_REGISTER__MASK 0xFFFFFFFF -#define VAP_PVS_STATE_FLUSH_REG__DATA_REGISTER__SHIFT 0 - -/* packet stuff **************************************************************/ -#define PACKET_HEADER_MASK 0xC0000000 -#define PACKET_HEADER_SHIFT 30 -#define PACKET_HEADER_GET(p) (((p) & PACKET_HEADER_MASK) >> PACKET_HEADER_SHIFT) -#define PACKET_HEADER_SET(p) (((p) << PACKET_HEADER_SHIFT) & PACKET_HEADER_MASK) - -#define PACKET0_HEADER 0x0 -# define PACKET0_REG_MASK 0x00001FFF -# define PACKET0_REG_SHIFT 0 -# define PACKET0_COUNT_MASK 0x3FFF0000 -# define PACKET0_COUNT_SHIFT 16 -#define PACKET1_HEADER 0x1 -#define PACKET2_HEADER 0x2 -#define PACKET3_HEADER 0x3 -# define PACKET3_OPCODE_MASK 0x0000FF00 -# define PACKET3_OPCODE_SHIFT 8 -# define PACKET3_OPCODE_NOP 0x10 -# define PACKET3_OPCODE_BITBLT 0x92 -# define PACKET3_OPCODE_BITBLT_MULTI 0x9B -# define PACKET3_COUNT_MASK 0x3FFF0000 -# define PACKET3_COUNT_SHIFT 16 - -#define CP_PACKET0(r, n) (PACKET_HEADER_SET(PACKET0_HEADER) |\ - ((((r)>>2)<<PACKET0_REG_SHIFT) & PACKET0_REG_MASK) |\ - (((n) << PACKET0_COUNT_SHIFT) & PACKET0_COUNT_MASK)) -#define CP_PACKET3(o, n) (PACKET_HEADER_SET(PACKET3_HEADER) |\ - (((o)<<PACKET3_OPCODE_SHIFT) & PACKET3_OPCODE_MASK) |\ - (((n)<<PACKET3_COUNT_SHIFT) & PACKET3_COUNT_MASK)) - -#endif |