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Diffstat (limited to 'shared-core/radeon_ms_drm.h')
| -rw-r--r-- | shared-core/radeon_ms_drm.h | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/shared-core/radeon_ms_drm.h b/shared-core/radeon_ms_drm.h new file mode 100644 index 00000000..842d5331 --- /dev/null +++ b/shared-core/radeon_ms_drm.h @@ -0,0 +1,60 @@ +/* + * Copyright 2007 Jérôme Glisse + * Copyright 2007 Dave Airlie + * Copyright 2007 Alex Deucher + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +/* + * Authors: + * Jérôme Glisse <glisse@freedesktop.org> + */ +#ifndef __RADEON_MS_DRM_H__ +#define __RADEON_MS_DRM_H__ + +/* fence definitions */ +/* The only fence class we support */ +#define DRM_RADEON_FENCE_CLASS_ACCEL 0 +/* Fence type that guarantees read-write flush */ +#define DRM_RADEON_FENCE_TYPE_RW 2 +/* cache flushes programmed just before the fence */ +#define DRM_RADEON_FENCE_FLAG_FLUSHED 0x01000000 + +/* radeon ms ioctl */ +#define DRM_RADEON_EXECBUFFER 0x00 + +struct drm_radeon_execbuffer_arg { + uint64_t next; + uint32_t reloc_offset; + union { + struct drm_bo_op_req req; + struct drm_bo_arg_rep rep; + } d; +}; + +struct drm_radeon_execbuffer { + uint32_t args_count; + uint64_t args; + uint32_t cmd_size; + struct drm_fence_arg fence_arg; +}; + +#endif |