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Diffstat (limited to 'shared-core/nv40_graph.c')
-rw-r--r--shared-core/nv40_graph.c30
1 files changed, 14 insertions, 16 deletions
diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c
index 00583cdc..659767f2 100644
--- a/shared-core/nv40_graph.c
+++ b/shared-core/nv40_graph.c
@@ -611,10 +611,9 @@ nv40_graph_context_create(drm_device_t *dev, int channel)
struct nouveau_fifo *chan = &dev_priv->fifos[channel];
void (*ctx_init)(drm_device_t *, struct mem_block *);
unsigned int ctx_size;
- int i, chipset;
+ int i;
- chipset = (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000) >> 20;
- switch (chipset) {
+ switch (dev_priv->chipset) {
case 0x40:
ctx_size = NV40_GRCTX_SIZE;
ctx_init = nv40_graph_context_init;
@@ -665,11 +664,11 @@ nv40_graph_context_save_current(drm_device_t *dev)
uint32_t instance;
int i;
- NV_WRITE(NV_PGRAPH_FIFO, 0);
+ NV_WRITE(NV04_PGRAPH_FIFO, 0);
instance = NV_READ(0x40032C) & 0xFFFFF;
if (!instance) {
- NV_WRITE(NV_PGRAPH_FIFO, 1);
+ NV_WRITE(NV04_PGRAPH_FIFO, 1);
return;
}
@@ -685,11 +684,11 @@ nv40_graph_context_save_current(drm_device_t *dev)
DRM_ERROR("failed to save current grctx to ramin\n");
DRM_ERROR("instance = 0x%08x\n", NV_READ(0x40032C));
DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(0x40030C));
- NV_WRITE(NV_PGRAPH_FIFO, 1);
+ NV_WRITE(NV04_PGRAPH_FIFO, 1);
return;
}
- NV_WRITE(NV_PGRAPH_FIFO, 1);
+ NV_WRITE(NV04_PGRAPH_FIFO, 1);
}
/* Restore the context for a specific channel into PGRAPH
@@ -706,7 +705,7 @@ nv40_graph_context_restore(drm_device_t *dev, int channel)
instance = nouveau_chip_instance_get(dev, chan->ramin_grctx);
- NV_WRITE(NV_PGRAPH_FIFO, 0);
+ NV_WRITE(NV04_PGRAPH_FIFO, 0);
NV_WRITE(0x400784, instance);
NV_WRITE(0x400310, NV_READ(0x400310) | 0x40);
NV_WRITE(0x400304, 1);
@@ -720,7 +719,7 @@ nv40_graph_context_restore(drm_device_t *dev, int channel)
channel);
DRM_ERROR("instance = 0x%08x\n", instance);
DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(0x40030C));
- NV_WRITE(NV_PGRAPH_FIFO, 1);
+ NV_WRITE(NV04_PGRAPH_FIFO, 1);
return;
}
@@ -736,7 +735,7 @@ nv40_graph_context_restore(drm_device_t *dev, int channel)
* recieve PGRAPH_INTR_CONTEXT_SWITCH
*/
NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE, instance);
- NV_WRITE(NV_PGRAPH_FIFO, 1);
+ NV_WRITE(NV04_PGRAPH_FIFO, 1);
}
/* Some voodoo that makes context switching work without the binary driver
@@ -896,17 +895,16 @@ nv40_graph_init(drm_device_t *dev)
(drm_nouveau_private_t *)dev->dev_private;
uint32_t *ctx_voodoo;
uint32_t pg0220_inst;
- int i, chipset;
+ int i;
- chipset = (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000) >> 20;
- DRM_DEBUG("chipset (from PMC_BOOT_0): NV%02X\n", chipset);
- switch (chipset) {
+ switch (dev_priv->chipset) {
case 0x40: ctx_voodoo = nv40_ctx_voodoo; break;
case 0x43: ctx_voodoo = nv43_ctx_voodoo; break;
case 0x4a: ctx_voodoo = nv4a_ctx_voodoo; break;
case 0x4e: ctx_voodoo = nv4e_ctx_voodoo; break;
default:
- DRM_ERROR("Unknown ctx_voodoo for chipset 0x%02x\n", chipset);
+ DRM_ERROR("Unknown ctx_voodoo for chipset 0x%02x\n",
+ dev_priv->chipset);
ctx_voodoo = NULL;
break;
}
@@ -932,7 +930,7 @@ nv40_graph_init(drm_device_t *dev)
NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM);
pg0220_inst = nouveau_chip_instance_get(dev,
dev_priv->fb_obj->instance);
- NV_WRITE(NV_PGRAPH_NV40_UNK220, pg0220_inst);
+ NV_WRITE(NV40_PGRAPH_UNK220, pg0220_inst);
return 0;
}