diff options
Diffstat (limited to 'shared-core/nv04_fifo.c')
-rw-r--r-- | shared-core/nv04_fifo.c | 63 |
1 files changed, 33 insertions, 30 deletions
diff --git a/shared-core/nv04_fifo.c b/shared-core/nv04_fifo.c index bfae432e..d750ced8 100644 --- a/shared-core/nv04_fifo.c +++ b/shared-core/nv04_fifo.c @@ -28,31 +28,31 @@ #include "drm.h" #include "nouveau_drv.h" -#define RAMFC_WR(offset, val) NV_WI32(fifoctx + NV04_RAMFC_##offset, (val)) -#define RAMFC_RD(offset) NV_RI32(fifoctx + NV04_RAMFC_##offset) +#define RAMFC_WR(offset,val) INSTANCE_WR(chan->ramfc->gpuobj, \ + NV04_RAMFC_##offset/4, (val)) +#define RAMFC_RD(offset) INSTANCE_RD(chan->ramfc->gpuobj, \ + NV04_RAMFC_##offset/4) #define NV04_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV04_RAMFC__SIZE)) #define NV04_RAMFC__SIZE 32 int -nv04_fifo_create_context(drm_device_t *dev, int channel) +nv04_fifo_create_context(struct nouveau_channel *chan) { - drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; - struct nouveau_object *pb = chan->cmdbuf_obj; - uint32_t fifoctx = NV04_RAMFC(channel); - int i; - - if (!pb || !pb->instance) - return DRM_ERR(EINVAL); - - /* Clear RAMFC */ - for (i=0; i<NV04_RAMFC__SIZE; i+=4) - NV_WI32(fifoctx + i, 0); - + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; + int ret; + + if ((ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(chan->id), ~0, + NV04_RAMFC__SIZE, + NVOBJ_FLAG_ZERO_ALLOC | + NVOBJ_FLAG_ZERO_FREE, + NULL, &chan->ramfc))) + return ret; + /* Setup initial state */ RAMFC_WR(DMA_PUT, chan->pushbuf_base); RAMFC_WR(DMA_GET, chan->pushbuf_base); - RAMFC_WR(DMA_INSTANCE, nouveau_chip_instance_get(dev, pb->instance)); + RAMFC_WR(DMA_INSTANCE, chan->pushbuf->instance >> 4); RAMFC_WR(DMA_FETCH, (NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 | @@ -60,28 +60,31 @@ nv04_fifo_create_context(drm_device_t *dev, int channel) NV_PFIFO_CACHE1_BIG_ENDIAN | #endif 0)); + + /* enable the fifo dma operation */ + NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE) | (1<<chan->id)); return 0; } void -nv04_fifo_destroy_context(drm_device_t *dev, int channel) +nv04_fifo_destroy_context(struct nouveau_channel *chan) { - drm_nouveau_private_t *dev_priv = dev->dev_private; - uint32_t fifoctx = NV04_RAMFC(channel); - int i; + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; + + NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<chan->id)); - for (i=0; i<NV04_RAMFC__SIZE; i+=4) - NV_WI32(fifoctx + i, 0); + nouveau_gpuobj_ref_del(dev, &chan->ramfc); } int -nv04_fifo_load_context(drm_device_t *dev, int channel) +nv04_fifo_load_context(struct nouveau_channel *chan) { - drm_nouveau_private_t *dev_priv = dev->dev_private; - uint32_t fifoctx = NV04_RAMFC(channel); + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t tmp; - NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, (1<<8) | channel); + NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, (1<<8) | chan->id); NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, RAMFC_RD(DMA_GET)); NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, RAMFC_RD(DMA_PUT)); @@ -103,10 +106,10 @@ nv04_fifo_load_context(drm_device_t *dev, int channel) } int -nv04_fifo_save_context(drm_device_t *dev, int channel) +nv04_fifo_save_context(struct nouveau_channel *chan) { - drm_nouveau_private_t *dev_priv = dev->dev_private; - uint32_t fifoctx = NV04_RAMFC(channel); + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t tmp; RAMFC_WR(DMA_PUT, NV04_PFIFO_CACHE1_DMA_PUT); |