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Diffstat (limited to 'linux-core')
-rw-r--r--linux-core/drm_crtc.c24
-rw-r--r--linux-core/intel_display.c21
2 files changed, 16 insertions, 29 deletions
diff --git a/linux-core/drm_crtc.c b/linux-core/drm_crtc.c
index 63ad829d..259ea1b8 100644
--- a/linux-core/drm_crtc.c
+++ b/linux-core/drm_crtc.c
@@ -254,8 +254,7 @@ bool drm_crtc_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
/* Now, enable the clocks, plane, pipe, and outputs that we set up. */
crtc->funcs->commit(crtc);
list_for_each_entry(output, &dev->mode_config.output_list, head) {
- if (output->crtc == crtc)
- {
+ if (output->crtc == crtc) {
output->funcs->commit(output);
#if 0 // TODO def RANDR_12_INTERFACE
if (output->randr_output)
@@ -624,8 +623,7 @@ int drm_crtc_set_config(struct drm_crtc *crtc, struct drm_mode_crtc *crtc_info,
else
new_crtc = output->crtc;
- for (ro = 0; ro < crtc_info->count_outputs; ro++)
- {
+ for (ro = 0; ro < crtc_info->count_outputs; ro++) {
if (output_set[ro] == output)
new_crtc = crtc;
}
@@ -913,8 +911,7 @@ int drm_mode_setcrtc(struct inode *inode, struct file *filp,
return -EFAULT;
crtc = idr_find(&dev->mode_config.crtc_idr, crtc_req.crtc_id);
- if (!crtc || (crtc->id != crtc_req.crtc_id))
- {
+ if (!crtc || (crtc->id != crtc_req.crtc_id)) {
DRM_DEBUG("Unknown CRTC ID %d\n", crtc_req.crtc_id);
return -EINVAL;
}
@@ -930,15 +927,12 @@ int drm_mode_setcrtc(struct inode *inode, struct file *filp,
}
}
mode = idr_find(&dev->mode_config.crtc_idr, crtc_req.mode);
- if (!mode || (mode->mode_id != crtc_req.mode))
- {
- {
- struct drm_output *output;
-
- list_for_each_entry(output, &dev->mode_config.output_list, head) {
- list_for_each_entry(mode, &output->modes, head) {
- drm_mode_debug_printmodeline(dev, mode);
- }
+ if (!mode || (mode->mode_id != crtc_req.mode)) {
+ struct drm_output *output;
+
+ list_for_each_entry(output, &dev->mode_config.output_list, head) {
+ list_for_each_entry(mode, &output->modes, head) {
+ drm_mode_debug_printmodeline(dev, mode);
}
}
diff --git a/linux-core/intel_display.c b/linux-core/intel_display.c
index 396f4cfa..aed86231 100644
--- a/linux-core/intel_display.c
+++ b/linux-core/intel_display.c
@@ -412,8 +412,7 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
case DPMSModeSuspend:
/* Enable the DPLL */
temp = I915_READ(dpll_reg);
- if ((temp & DPLL_VCO_ENABLE) == 0)
- {
+ if ((temp & DPLL_VCO_ENABLE) == 0) {
I915_WRITE(dpll_reg, temp);
I915_READ(dpll_reg);
/* Wait for the clocks to stabilize. */
@@ -435,8 +434,7 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
/* Enable the plane */
temp = I915_READ(dspcntr_reg);
- if ((temp & DISPLAY_PLANE_ENABLE) == 0)
- {
+ if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
/* Flush the plane changes */
I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
@@ -456,8 +454,7 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
/* Disable display plane */
temp = I915_READ(dspcntr_reg);
- if ((temp & DISPLAY_PLANE_ENABLE) != 0)
- {
+ if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
/* Flush the plane changes */
I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
@@ -719,11 +716,9 @@ static void intel_crtc_mode_set(struct drm_crtc *crtc,
dpll |= DPLLB_MODE_LVDS;
else
dpll |= DPLLB_MODE_DAC_SERIAL;
- if (is_sdvo)
- {
+ if (is_sdvo) {
dpll |= DPLL_DVO_HIGH_SPEED;
- if (IS_I945G(dev) || IS_I945GM(dev))
- {
+ if (IS_I945G(dev) || IS_I945GM(dev)) {
int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
}
@@ -760,8 +755,7 @@ static void intel_crtc_mode_set(struct drm_crtc *crtc,
}
}
- if (is_tv)
- {
+ if (is_tv) {
/* XXX: just matching BIOS for now */
/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
dpll |= 3;
@@ -801,8 +795,7 @@ static void intel_crtc_mode_set(struct drm_crtc *crtc,
dspcntr |= DISPPLANE_SEL_PIPE_B;
pipeconf = I915_READ(pipeconf_reg);
- if (pipe == 0 && !IS_I965G(dev))
- {
+ if (pipe == 0 && !IS_I965G(dev)) {
/* Enable pixel doubling when the dot clock is > 90% of the (display)
* core speed.
*