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-rw-r--r--linux-core/drmP.h10
l---------linux-core/drm_internal.h1
-rw-r--r--linux-core/drm_sysfs.c2
-rw-r--r--linux-core/i915_compat.c124
-rw-r--r--linux-core/i915_drv.c11
-rw-r--r--linux-core/nouveau_fence.c3
6 files changed, 109 insertions, 42 deletions
diff --git a/linux-core/drmP.h b/linux-core/drmP.h
index 3d30ec7d..208b48f4 100644
--- a/linux-core/drmP.h
+++ b/linux-core/drmP.h
@@ -83,6 +83,7 @@
#include "drm_os_linux.h"
#include "drm_hashtab.h"
+#include "drm_internal.h"
struct drm_file;
@@ -590,15 +591,6 @@ struct drm_vbl_sig {
struct task_struct *task;
};
-/**
- * Drawable information.
- */
-struct drm_drawable_info {
- unsigned int num_rects;
- struct drm_clip_rect *rects;
-};
-
-
/* location of GART table */
#define DRM_ATI_GART_MAIN 1
#define DRM_ATI_GART_FB 2
diff --git a/linux-core/drm_internal.h b/linux-core/drm_internal.h
new file mode 120000
index 00000000..b30ef94a
--- /dev/null
+++ b/linux-core/drm_internal.h
@@ -0,0 +1 @@
+../shared-core/drm_internal.h \ No newline at end of file
diff --git a/linux-core/drm_sysfs.c b/linux-core/drm_sysfs.c
index 6f8623ce..caec120a 100644
--- a/linux-core/drm_sysfs.c
+++ b/linux-core/drm_sysfs.c
@@ -89,8 +89,10 @@ struct class *drm_sysfs_create(struct module *owner, char *name)
goto err_out;
}
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22))
class->suspend = drm_sysfs_suspend;
class->resume = drm_sysfs_resume;
+#endif
err = class_create_file(class, &class_attr_version);
if (err)
diff --git a/linux-core/i915_compat.c b/linux-core/i915_compat.c
index b09cc9f2..e119a992 100644
--- a/linux-core/i915_compat.c
+++ b/linux-core/i915_compat.c
@@ -19,10 +19,15 @@
#define I915_IFPADDR 0x60
#define I965_IFPADDR 0x70
-static struct _intel_private_compat {
+static struct _i9xx_private_compat {
void __iomem *flush_page;
struct resource ifp_resource;
-} intel_private;
+} i9xx_private;
+
+static struct _i8xx_private_compat {
+ void *flush_page;
+ struct page *page;
+} i8xx_private;
static void
intel_compat_align_resource(void *data, struct resource *res,
@@ -35,7 +40,7 @@ intel_compat_align_resource(void *data, struct resource *res,
static int intel_alloc_chipset_flush_resource(struct pci_dev *pdev)
{
int ret;
- ret = pci_bus_alloc_resource(pdev->bus, &intel_private.ifp_resource, PAGE_SIZE,
+ ret = pci_bus_alloc_resource(pdev->bus, &i9xx_private.ifp_resource, PAGE_SIZE,
PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
intel_compat_align_resource, pdev);
if (ret != 0)
@@ -53,15 +58,15 @@ static void intel_i915_setup_chipset_flush(struct pci_dev *pdev)
if (!(temp & 0x1)) {
intel_alloc_chipset_flush_resource(pdev);
- pci_write_config_dword(pdev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
+ pci_write_config_dword(pdev, I915_IFPADDR, (i9xx_private.ifp_resource.start & 0xffffffff) | 0x1);
} else {
temp &= ~1;
- intel_private.ifp_resource.start = temp;
- intel_private.ifp_resource.end = temp + PAGE_SIZE;
- ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
+ i9xx_private.ifp_resource.start = temp;
+ i9xx_private.ifp_resource.end = temp + PAGE_SIZE;
+ ret = request_resource(&iomem_resource, &i9xx_private.ifp_resource);
if (ret) {
- intel_private.ifp_resource.start = 0;
+ i9xx_private.ifp_resource.start = 0;
printk("Failed inserting resource into tree\n");
}
}
@@ -79,34 +84,70 @@ static void intel_i965_g33_setup_chipset_flush(struct pci_dev *pdev)
intel_alloc_chipset_flush_resource(pdev);
- pci_write_config_dword(pdev, I965_IFPADDR + 4, (intel_private.ifp_resource.start >> 32));
- pci_write_config_dword(pdev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
+ pci_write_config_dword(pdev, I965_IFPADDR + 4, (i9xx_private.ifp_resource.start >> 32));
+ pci_write_config_dword(pdev, I965_IFPADDR, (i9xx_private.ifp_resource.start & 0xffffffff) | 0x1);
} else {
u64 l64;
temp_lo &= ~0x1;
l64 = ((u64)temp_hi << 32) | temp_lo;
- intel_private.ifp_resource.start = l64;
- intel_private.ifp_resource.end = l64 + PAGE_SIZE;
- ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
+ i9xx_private.ifp_resource.start = l64;
+ i9xx_private.ifp_resource.end = l64 + PAGE_SIZE;
+ ret = request_resource(&iomem_resource, &i9xx_private.ifp_resource);
if (!ret) {
- intel_private.ifp_resource.start = 0;
+ i9xx_private.ifp_resource.start = 0;
printk("Failed inserting resource into tree\n");
}
}
}
-void intel_init_chipset_flush_compat(struct drm_device *dev)
+static void intel_i8xx_fini_flush(struct drm_device *dev)
{
- struct pci_dev *agp_dev = dev->agp->agp_info.device;
+ kunmap(i8xx_private.page);
+ i8xx_private.flush_page = NULL;
+ unmap_page_from_agp(i8xx_private.page);
+ flush_agp_mappings();
- /* not flush on i8xx */
- if (!IS_I9XX(dev))
+ __free_page(i8xx_private.page);
+}
+
+static void intel_i8xx_setup_flush(struct drm_device *dev)
+{
+
+ i8xx_private.page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
+ if (!i8xx_private.page) {
return;
+ }
+
+ /* make page uncached */
+ map_page_into_agp(i8xx_private.page);
+ flush_agp_mappings();
+
+ i8xx_private.flush_page = kmap(i8xx_private.page);
+ if (!i8xx_private.flush_page)
+ intel_i8xx_fini_flush(dev);
+}
+
+
+static void intel_i8xx_flush_page(struct drm_device *dev)
+{
+ unsigned int *pg = i8xx_private.flush_page;
+ int i;
+
+ /* HAI NUT CAN I HAZ HAMMER?? */
+ for (i = 0; i < 256; i++)
+ *(pg + i) = i;
+
+ DRM_MEMORYBARRIER();
+}
- intel_private.ifp_resource.name = "GMCH IFPBAR";
- intel_private.ifp_resource.flags = IORESOURCE_MEM;
+static void intel_i9xx_setup_flush(struct drm_device *dev)
+{
+ struct pci_dev *agp_dev = dev->agp->agp_info.device;
+
+ i9xx_private.ifp_resource.name = "GMCH IFPBAR";
+ i9xx_private.ifp_resource.flags = IORESOURCE_MEM;
/* Setup chipset flush for 915 */
if (IS_I965G(dev) || IS_G33(dev)) {
@@ -115,26 +156,49 @@ void intel_init_chipset_flush_compat(struct drm_device *dev)
intel_i915_setup_chipset_flush(agp_dev);
}
- if (intel_private.ifp_resource.start) {
- intel_private.flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
- if (!intel_private.flush_page)
+ if (i9xx_private.ifp_resource.start) {
+ i9xx_private.flush_page = ioremap_nocache(i9xx_private.ifp_resource.start, PAGE_SIZE);
+ if (!i9xx_private.flush_page)
printk("unable to ioremap flush page - no chipset flushing");
}
}
-void intel_fini_chipset_flush_compat(struct drm_device *dev)
+static void intel_i9xx_fini_flush(struct drm_device *dev)
+{
+ iounmap(i9xx_private.flush_page);
+ release_resource(&i9xx_private.ifp_resource);
+}
+
+static void intel_i9xx_flush_page(struct drm_device *dev)
+{
+ if (i9xx_private.flush_page)
+ writel(1, i9xx_private.flush_page);
+}
+
+void intel_init_chipset_flush_compat(struct drm_device *dev)
{
/* not flush on i8xx */
- if (!IS_I9XX(dev))
- return;
+ if (IS_I9XX(dev))
+ intel_i9xx_setup_flush(dev);
+ else
+ intel_i8xx_setup_flush(dev);
+
+}
- iounmap(intel_private.flush_page);
- release_resource(&intel_private.ifp_resource);
+void intel_fini_chipset_flush_compat(struct drm_device *dev)
+{
+ /* not flush on i8xx */
+ if (IS_I9XX(dev))
+ intel_i9xx_fini_flush(dev);
+ else
+ intel_i8xx_fini_flush(dev);
}
void drm_agp_chipset_flush(struct drm_device *dev)
{
- if (intel_private.flush_page)
- writel(1, intel_private.flush_page);
+ if (IS_I9XX(dev))
+ intel_i9xx_flush_page(dev);
+ else
+ intel_i8xx_flush_page(dev);
}
#endif
diff --git a/linux-core/i915_drv.c b/linux-core/i915_drv.c
index 74b4c32e..fb4149c4 100644
--- a/linux-core/i915_drv.c
+++ b/linux-core/i915_drv.c
@@ -432,7 +432,11 @@ static int i915_resume(struct drm_device *dev)
I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
}
- I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
+
+ if ((dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) &&
+ (dev_priv->saveDPLL_A & DPLL_VGA_MODE_DIS))
+ I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
+
i915_restore_palette(dev, PIPE_A);
/* Enable the plane */
I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
@@ -472,7 +476,10 @@ static int i915_resume(struct drm_device *dev)
I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
}
- I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
+
+ if ((dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) &&
+ (dev_priv->saveDPLL_B & DPLL_VGA_MODE_DIS))
+ I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
i915_restore_palette(dev, PIPE_A);
/* Enable the plane */
I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
diff --git a/linux-core/nouveau_fence.c b/linux-core/nouveau_fence.c
index b3e81a89..4e624a7a 100644
--- a/linux-core/nouveau_fence.c
+++ b/linux-core/nouveau_fence.c
@@ -79,6 +79,7 @@ nouveau_fence_perform_flush(struct drm_device *dev, uint32_t class)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct drm_fence_class_manager *fc = &dev->fm.fence_class[class];
+ struct nouveau_channel *chan = dev_priv->fifos[class];
uint32_t pending_types = 0;
DRM_DEBUG("class=%d\n", class);
@@ -89,7 +90,7 @@ nouveau_fence_perform_flush(struct drm_device *dev, uint32_t class)
fc->pending_flush);
if (pending_types) {
- uint32_t sequence = NV_READ(NV03_FIFO_REGS(class) + 0x48);
+ uint32_t sequence = NV_READ(chan->ref_cnt);
DRM_DEBUG("got 0x%08x\n", sequence);
drm_fence_handler(dev, class, sequence, pending_types, 0);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-03 04:10:44 +0000