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-rw-r--r--linux-core/i915_drv.c59
-rw-r--r--linux-core/i915_fence.c2
-rw-r--r--linux-core/intel_display.c52
-rw-r--r--linux-core/intel_lvds.c12
-rw-r--r--linux-core/intel_tv.c18
5 files changed, 62 insertions, 81 deletions
diff --git a/linux-core/i915_drv.c b/linux-core/i915_drv.c
index ec91fb93..27c239d0 100644
--- a/linux-core/i915_drv.c
+++ b/linux-core/i915_drv.c
@@ -67,11 +67,6 @@ static struct drm_bo_driver i915_bo_driver = {
};
#endif
-enum pipe {
- PIPE_A = 0,
- PIPE_B,
-};
-
static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -308,13 +303,13 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
- dev_priv->saveDSPABASE = I915_READ(DSPABASE);
+ dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);
if (IS_I965G(dev)) {
dev_priv->saveDSPASURF = I915_READ(DSPASURF);
dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
}
i915_save_palette(dev, PIPE_A);
- dev_priv->savePIPEASTAT = I915_READ(I915REG_PIPEASTAT);
+ dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);
/* Pipe & plane B info */
dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
@@ -336,13 +331,13 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
- dev_priv->saveDSPBBASE = I915_READ(DSPBBASE);
+ dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);
if (IS_I965GM(dev) || IS_IGD_GM(dev)) {
dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
}
i915_save_palette(dev, PIPE_B);
- dev_priv->savePIPEBSTAT = I915_READ(I915REG_PIPEBSTAT);
+ dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
/* CRT state */
dev_priv->saveADPA = I915_READ(ADPA);
@@ -357,9 +352,9 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
dev_priv->saveLVDS = I915_READ(LVDS);
if (!IS_I830(dev) && !IS_845G(dev))
dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
- dev_priv->saveLVDSPP_ON = I915_READ(LVDSPP_ON);
- dev_priv->saveLVDSPP_OFF = I915_READ(LVDSPP_OFF);
- dev_priv->savePP_CYCLE = I915_READ(PP_CYCLE);
+ dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
+ dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
+ dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
/* FIXME: save TV & SDVO state */
@@ -370,19 +365,19 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
/* Interrupt state */
- dev_priv->saveIIR = I915_READ(I915REG_INT_IDENTITY_R);
- dev_priv->saveIER = I915_READ(I915REG_INT_ENABLE_R);
- dev_priv->saveIMR = I915_READ(I915REG_INT_MASK_R);
+ dev_priv->saveIIR = I915_READ(IIR);
+ dev_priv->saveIER = I915_READ(IER);
+ dev_priv->saveIMR = I915_READ(IMR);
/* VGA state */
- dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
- dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);
- dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV);
+ dev_priv->saveVGA0 = I915_READ(VGA0);
+ dev_priv->saveVGA1 = I915_READ(VGA1);
+ dev_priv->saveVGA_PD = I915_READ(VGA_PD);
dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
/* Clock gating state */
dev_priv->saveD_STATE = I915_READ(D_STATE);
- dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
+ dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS);
/* Cache mode state */
dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
@@ -419,6 +414,8 @@ static int i915_resume(struct drm_device *dev)
if (pci_enable_device(dev->pdev))
return -1;
+ DRM_INFO("resuming i915\n");
+
pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
I915_WRITE(DSPARB, dev_priv->saveDSPARB);
@@ -452,7 +449,7 @@ static int i915_resume(struct drm_device *dev)
I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
- I915_WRITE(DSPABASE, dev_priv->saveDSPABASE);
+ I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
if (IS_I965G(dev)) {
I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
@@ -464,10 +461,11 @@ static int i915_resume(struct drm_device *dev)
i915_restore_palette(dev, PIPE_A);
/* Enable the plane */
I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
- I915_WRITE(DSPABASE, I915_READ(DSPABASE));
+ I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
/* Pipe & plane B info */
if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
+ DRM_INFO("restoring DPLL_B: 0x%08x\n", dev_priv->saveDPLL_B);
I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
~DPLL_VCO_ENABLE);
udelay(150);
@@ -476,6 +474,7 @@ static int i915_resume(struct drm_device *dev)
I915_WRITE(FPB1, dev_priv->saveFPB1);
/* Actually enable it */
I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
+ DRM_INFO("restoring DPLL_B: 0x%08x\n", dev_priv->saveDPLL_B);
udelay(150);
if (IS_I965G(dev))
I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
@@ -494,7 +493,7 @@ static int i915_resume(struct drm_device *dev)
I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
- I915_WRITE(DSPBBASE, dev_priv->saveDSPBBASE);
+ I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
if (IS_I965G(dev)) {
I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
@@ -506,7 +505,7 @@ static int i915_resume(struct drm_device *dev)
i915_restore_palette(dev, PIPE_B);
/* Enable the plane */
I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
- I915_WRITE(DSPBBASE, I915_READ(DSPBBASE));
+ I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
/* CRT state */
I915_WRITE(ADPA, dev_priv->saveADPA);
@@ -521,9 +520,9 @@ static int i915_resume(struct drm_device *dev)
I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
- I915_WRITE(LVDSPP_ON, dev_priv->saveLVDSPP_ON);
- I915_WRITE(LVDSPP_OFF, dev_priv->saveLVDSPP_OFF);
- I915_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE);
+ I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
+ I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
+ I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
/* FIXME: restore TV & SDVO state */
@@ -536,14 +535,14 @@ static int i915_resume(struct drm_device *dev)
/* VGA state */
I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
- I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv->saveVCLK_DIVISOR_VGA0);
- I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv->saveVCLK_DIVISOR_VGA1);
- I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV);
+ I915_WRITE(VGA0, dev_priv->saveVGA0);
+ I915_WRITE(VGA1, dev_priv->saveVGA1);
+ I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
udelay(150);
/* Clock gating state */
I915_WRITE (D_STATE, dev_priv->saveD_STATE);
- I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
+ I915_WRITE (CG_2D_DIS, dev_priv->saveCG_2D_DIS);
/* Cache mode state */
I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
diff --git a/linux-core/i915_fence.c b/linux-core/i915_fence.c
index 3ca8403f..436b7e1f 100644
--- a/linux-core/i915_fence.c
+++ b/linux-core/i915_fence.c
@@ -46,7 +46,7 @@ static inline void i915_initiate_rwflush(struct drm_i915_private *dev_priv,
dev_priv->flush_sequence = (uint32_t) READ_BREADCRUMB(dev_priv);
dev_priv->flush_flags = fc->pending_flush;
dev_priv->saved_flush_status = READ_HWSP(dev_priv, 0);
- I915_WRITE(I915REG_INSTPM, (1 << 5) | (1 << 21));
+ I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
dev_priv->flush_pending = 1;
fc->pending_flush &= ~DRM_I915_FENCE_TYPE_RW;
}
diff --git a/linux-core/intel_display.c b/linux-core/intel_display.c
index f66570c2..273f76d0 100644
--- a/linux-core/intel_display.c
+++ b/linux-core/intel_display.c
@@ -367,7 +367,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y)
struct intel_crtc *intel_crtc = crtc->driver_private;
int pipe = intel_crtc->pipe;
unsigned long Start, Offset;
- int dspbase = (pipe == 0 ? DSPABASE : DSPBBASE);
+ int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
@@ -456,7 +456,7 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
int pipe = intel_crtc->pipe;
int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
- int dspbase_reg = (pipe == 0) ? DSPABASE : DSPBBASE;
+ int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
u32 temp;
bool enabled;
@@ -617,16 +617,16 @@ static int intel_get_core_clock_speed(struct drm_device *dev)
else if (IS_I915GM(dev)) {
u16 gcfgc = 0;
- pci_read_config_word(dev->pdev, I915_GCFGC, &gcfgc);
+ pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
- if (gcfgc & I915_LOW_FREQUENCY_ENABLE)
+ if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
return 133000;
else {
- switch (gcfgc & I915_DISPLAY_CLOCK_MASK) {
- case I915_DISPLAY_CLOCK_333_MHZ:
+ switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
+ case GC_DISPLAY_CLOCK_333_MHZ:
return 333000;
default:
- case I915_DISPLAY_CLOCK_190_200_MHZ:
+ case GC_DISPLAY_CLOCK_190_200_MHZ:
return 190000;
}
}
@@ -635,20 +635,20 @@ static int intel_get_core_clock_speed(struct drm_device *dev)
else if (IS_I855(dev)) {
#if 0
PCITAG bridge = pciTag(0, 0, 0); /* This is always the host bridge */
- u16 hpllcc = pciReadWord(bridge, I855_HPLLCC);
+ u16 hpllcc = pciReadWord(bridge, HPLLCC);
#endif
u16 hpllcc = 0;
/* Assume that the hardware is in the high speed state. This
* should be the default.
*/
- switch (hpllcc & I855_CLOCK_CONTROL_MASK) {
- case I855_CLOCK_133_200:
- case I855_CLOCK_100_200:
+ switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
+ case GC_CLOCK_133_200:
+ case GC_CLOCK_100_200:
return 200000;
- case I855_CLOCK_166_250:
+ case GC_CLOCK_166_250:
return 250000;
- case I855_CLOCK_100_133:
+ case GC_CLOCK_100_133:
return 133000;
}
} else /* 852, 830 */
@@ -961,24 +961,6 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
}
}
-#define CURSOR_A_CONTROL 0x70080
-#define CURSOR_A_BASE 0x70084
-#define CURSOR_A_POSITION 0x70088
-
-#define CURSOR_B_CONTROL 0x700C0
-#define CURSOR_B_BASE 0x700C4
-#define CURSOR_B_POSITION 0x700C8
-
-#define CURSOR_MODE_DISABLE 0x00
-#define CURSOR_MODE_64_32B_AX 0x07
-#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
-#define MCURSOR_GAMMA_ENABLE (1 << 26)
-
-#define CURSOR_POS_MASK 0x007FF
-#define CURSOR_POS_SIGN 0x8000
-#define CURSOR_X_SHIFT 0
-#define CURSOR_Y_SHIFT 16
-
static int intel_crtc_cursor_set(struct drm_crtc *crtc,
struct drm_buffer_object *bo,
uint32_t width, uint32_t height)
@@ -987,8 +969,8 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = crtc->driver_private;
int pipe = intel_crtc->pipe;
- uint32_t control = (pipe == 0) ? CURSOR_A_CONTROL : CURSOR_B_CONTROL;
- uint32_t base = (pipe == 0) ? CURSOR_A_BASE : CURSOR_B_BASE;
+ uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
+ uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
uint32_t temp;
size_t addr;
@@ -1063,8 +1045,8 @@ static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
adder = intel_crtc->cursor_addr;
- I915_WRITE((pipe == 0) ? CURSOR_A_POSITION : CURSOR_B_POSITION, temp);
- I915_WRITE((pipe == 0) ? CURSOR_A_BASE : CURSOR_B_BASE, adder);
+ I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
+ I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
return 0;
}
diff --git a/linux-core/intel_lvds.c b/linux-core/intel_lvds.c
index 92a1d600..1da95e18 100644
--- a/linux-core/intel_lvds.c
+++ b/linux-core/intel_lvds.c
@@ -106,10 +106,10 @@ static void intel_lvds_save(struct drm_output *output)
struct drm_device *dev = output->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- dev_priv->savePP_ON = I915_READ(LVDSPP_ON);
- dev_priv->savePP_OFF = I915_READ(LVDSPP_OFF);
+ dev_priv->savePP_ON = I915_READ(PP_ON_DELAYS);
+ dev_priv->savePP_OFF = I915_READ(PP_OFF_DELAYS);
dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
- dev_priv->savePP_CYCLE = I915_READ(PP_CYCLE);
+ dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL &
BACKLIGHT_DUTY_CYCLE_MASK);
@@ -128,9 +128,9 @@ static void intel_lvds_restore(struct drm_output *output)
struct drm_i915_private *dev_priv = dev->dev_private;
I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
- I915_WRITE(LVDSPP_ON, dev_priv->savePP_ON);
- I915_WRITE(LVDSPP_OFF, dev_priv->savePP_OFF);
- I915_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE);
+ I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON);
+ I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF);
+ I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
if (dev_priv->savePP_CONTROL & POWER_TARGET_ON)
intel_lvds_set_power(dev, true);
diff --git a/linux-core/intel_tv.c b/linux-core/intel_tv.c
index 865e27b9..42f4b10b 100644
--- a/linux-core/intel_tv.c
+++ b/linux-core/intel_tv.c
@@ -1012,7 +1012,7 @@ intel_tv_restore(struct drm_output *output)
int pipeconf = I915_READ(pipeconf_reg);
int dspcntr = I915_READ(dspcntr_reg);
int dspbase_reg = (intel_crtc->plane == 0) ?
- DSPABASE : DSPBBASE;
+ DSPAADDR : DSPBADDR;
/* Pipe must be off here */
I915_WRITE(dspcntr_reg, dspcntr & ~DISPLAY_PLANE_ENABLE);
/* Flush the plane changes */
@@ -1277,7 +1277,7 @@ intel_tv_mode_set(struct drm_output *output, struct drm_display_mode *mode,
int pipeconf = I915_READ(pipeconf_reg);
int dspcntr = I915_READ(dspcntr_reg);
int dspbase_reg = (intel_crtc->plane == 0) ?
- DSPABASE : DSPBBASE;
+ DSPAADDR : DSPBADDR;
int xpos = 0x0, ypos = 0x0;
unsigned int xsize, ysize;
/* Pipe must be off here */
@@ -1368,12 +1368,12 @@ intel_tv_detect_type (struct drm_crtc *crtc, struct drm_output *output)
tv_dac = I915_READ(TV_DAC);
/* Disable TV interrupts around load detect or we'll recurse */
- pipeastat = I915_READ(I915REG_PIPEASTAT);
+ pipeastat = I915_READ(PIPEASTAT);
pipeastat_save = pipeastat;
- pipeastat &= ~I915_HOTPLUG_INTERRUPT_ENABLE;
- pipeastat &= ~I915_HOTPLUG_TV_INTERRUPT_ENABLE;
- I915_WRITE(I915REG_PIPEASTAT, pipeastat | I915_HOTPLUG_TV_CLEAR |
- I915_HOTPLUG_CLEAR);
+ pipeastat &= ~PIPE_HOTPLUG_INTERRUPT_ENABLE;
+ pipeastat &= ~PIPE_HOTPLUG_TV_INTERRUPT_ENABLE;
+ I915_WRITE(PIPEASTAT, pipeastat | PIPE_HOTPLUG_TV_INTERRUPT_STATUS |
+ PIPE_HOTPLUG_INTERRUPT_STATUS);
/*
* Detect TV by polling)
@@ -1423,8 +1423,8 @@ intel_tv_detect_type (struct drm_crtc *crtc, struct drm_output *output)
}
/* Restore interrupt config */
- I915_WRITE(I915REG_PIPEASTAT, pipeastat_save | I915_HOTPLUG_TV_CLEAR |
- I915_HOTPLUG_CLEAR);
+ I915_WRITE(PIPEASTAT, pipeastat_save | PIPE_HOTPLUG_TV_INTERRUPT_STATUS |
+ PIPE_HOTPLUG_INTERRUPT_STATUS);
return type;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 15:26:38 +0000