diff options
Diffstat (limited to 'linux-core/i915_compat.c')
| -rw-r--r-- | linux-core/i915_compat.c | 126 |
1 files changed, 96 insertions, 30 deletions
diff --git a/linux-core/i915_compat.c b/linux-core/i915_compat.c index b09cc9f2..e8890f67 100644 --- a/linux-core/i915_compat.c +++ b/linux-core/i915_compat.c @@ -19,10 +19,15 @@ #define I915_IFPADDR 0x60 #define I965_IFPADDR 0x70 -static struct _intel_private_compat { +static struct _i9xx_private_compat { void __iomem *flush_page; struct resource ifp_resource; -} intel_private; +} i9xx_private; + +static struct _i8xx_private_compat { + void *flush_page; + struct page *page; +} i8xx_private; static void intel_compat_align_resource(void *data, struct resource *res, @@ -35,7 +40,7 @@ intel_compat_align_resource(void *data, struct resource *res, static int intel_alloc_chipset_flush_resource(struct pci_dev *pdev) { int ret; - ret = pci_bus_alloc_resource(pdev->bus, &intel_private.ifp_resource, PAGE_SIZE, + ret = pci_bus_alloc_resource(pdev->bus, &i9xx_private.ifp_resource, PAGE_SIZE, PAGE_SIZE, PCIBIOS_MIN_MEM, 0, intel_compat_align_resource, pdev); if (ret != 0) @@ -53,15 +58,15 @@ static void intel_i915_setup_chipset_flush(struct pci_dev *pdev) if (!(temp & 0x1)) { intel_alloc_chipset_flush_resource(pdev); - pci_write_config_dword(pdev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); + pci_write_config_dword(pdev, I915_IFPADDR, (i9xx_private.ifp_resource.start & 0xffffffff) | 0x1); } else { temp &= ~1; - intel_private.ifp_resource.start = temp; - intel_private.ifp_resource.end = temp + PAGE_SIZE; - ret = request_resource(&iomem_resource, &intel_private.ifp_resource); + i9xx_private.ifp_resource.start = temp; + i9xx_private.ifp_resource.end = temp + PAGE_SIZE; + ret = request_resource(&iomem_resource, &i9xx_private.ifp_resource); if (ret) { - intel_private.ifp_resource.start = 0; + i9xx_private.ifp_resource.start = 0; printk("Failed inserting resource into tree\n"); } } @@ -79,34 +84,72 @@ static void intel_i965_g33_setup_chipset_flush(struct pci_dev *pdev) intel_alloc_chipset_flush_resource(pdev); - pci_write_config_dword(pdev, I965_IFPADDR + 4, (intel_private.ifp_resource.start >> 32)); - pci_write_config_dword(pdev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); + pci_write_config_dword(pdev, I965_IFPADDR + 4, (i9xx_private.ifp_resource.start >> 32)); + pci_write_config_dword(pdev, I965_IFPADDR, (i9xx_private.ifp_resource.start & 0xffffffff) | 0x1); } else { u64 l64; temp_lo &= ~0x1; l64 = ((u64)temp_hi << 32) | temp_lo; - intel_private.ifp_resource.start = l64; - intel_private.ifp_resource.end = l64 + PAGE_SIZE; - ret = request_resource(&iomem_resource, &intel_private.ifp_resource); + i9xx_private.ifp_resource.start = l64; + i9xx_private.ifp_resource.end = l64 + PAGE_SIZE; + ret = request_resource(&iomem_resource, &i9xx_private.ifp_resource); if (!ret) { - intel_private.ifp_resource.start = 0; + i9xx_private.ifp_resource.start = 0; printk("Failed inserting resource into tree\n"); } } } -void intel_init_chipset_flush_compat(struct drm_device *dev) +static void intel_i8xx_fini_flush(struct drm_device *dev) { - struct pci_dev *agp_dev = dev->agp->agp_info.device; + kunmap(i8xx_private.page); + i8xx_private.flush_page = NULL; + unmap_page_from_agp(i8xx_private.page); + flush_agp_mappings(); - /* not flush on i8xx */ - if (!IS_I9XX(dev)) + __free_page(i8xx_private.page); +} + +static void intel_i8xx_setup_flush(struct drm_device *dev) +{ + + i8xx_private.page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32); + if (!i8xx_private.page) { return; + } - intel_private.ifp_resource.name = "GMCH IFPBAR"; - intel_private.ifp_resource.flags = IORESOURCE_MEM; + /* make page uncached */ + map_page_into_agp(i8xx_private.page); + flush_agp_mappings(); + + i8xx_private.flush_page = kmap(i8xx_private.page); + if (!i8xx_private.flush_page) + intel_i8xx_fini_flush(dev); + + DRM_ERROR("i8xx got flush page %p %p\n", i8xx_private.page, i8xx_private.flush_page); +} + + +static void intel_i8xx_flush_page(struct drm_device *dev) +{ + unsigned int *pg = i8xx_private.flush_page; + int i; + + /* HAI NUT CAN I HAZ HAMMER?? */ + for (i = 0; i < 256; i++) + *(pg + i) = i; + + DRM_MEMORYBARRIER(); +} + +static void intel_i9xx_setup_flush(struct drm_device *dev) +{ + struct pci_dev *agp_dev = dev->agp->agp_info.device; + + i9xx_private.ifp_resource.name = "GMCH IFPBAR"; + i9xx_private.ifp_resource.flags = IORESOURCE_MEM; /* Setup chipset flush for 915 */ if (IS_I965G(dev) || IS_G33(dev)) { @@ -115,26 +158,49 @@ void intel_init_chipset_flush_compat(struct drm_device *dev) intel_i915_setup_chipset_flush(agp_dev); } - if (intel_private.ifp_resource.start) { - intel_private.flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); - if (!intel_private.flush_page) + if (i9xx_private.ifp_resource.start) { + i9xx_private.flush_page = ioremap_nocache(i9xx_private.ifp_resource.start, PAGE_SIZE); + if (!i9xx_private.flush_page) printk("unable to ioremap flush page - no chipset flushing"); } } -void intel_fini_chipset_flush_compat(struct drm_device *dev) +static void intel_i9xx_fini_flush(struct drm_device *dev) +{ + iounmap(i9xx_private.flush_page); + release_resource(&i9xx_private.ifp_resource); +} + +static void intel_i9xx_flush_page(struct drm_device *dev) +{ + if (i9xx_private.flush_page) + writel(1, i9xx_private.flush_page); +} + +void intel_init_chipset_flush_compat(struct drm_device *dev) { /* not flush on i8xx */ - if (!IS_I9XX(dev)) - return; + if (IS_I9XX(dev)) + intel_i9xx_setup_flush(dev); + else + intel_i8xx_setup_flush(dev); + +} - iounmap(intel_private.flush_page); - release_resource(&intel_private.ifp_resource); +void intel_fini_chipset_flush_compat(struct drm_device *dev) +{ + /* not flush on i8xx */ + if (IS_I9XX(dev)) + intel_i9xx_fini_flush(dev); + else + intel_i8xx_fini_flush(dev); } void drm_agp_chipset_flush(struct drm_device *dev) { - if (intel_private.flush_page) - writel(1, intel_private.flush_page); + if (IS_I9XX(dev)) + intel_i9xx_flush_page(dev); + else + intel_i8xx_flush_page(dev); } #endif |