diff options
| -rw-r--r-- | shared-core/nouveau_fifo.c | 19 | ||||
| -rw-r--r-- | shared-core/nouveau_reg.h | 12 | ||||
| -rw-r--r-- | shared-core/nv04_graph.c | 27 |
3 files changed, 31 insertions, 27 deletions
diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index ca3b85c1..7f929c5c 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -197,16 +197,21 @@ int nouveau_fifo_init(drm_device_t *dev) NV_WRITE(NV04_PFIFO_CACHE1_PULL1, 0x00000001); /* FIXME on NV04 */ - NV_WRITE(NV10_PGRAPH_CTX_USER, 0x0); - NV_WRITE(NV04_PFIFO_DELAY_0, 0xff /* retrycount*/ ); - if (dev_priv->card_type >= NV_40) - NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x00002001); - else - NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10110000); + if (dev_priv->card_type >= NV_10) { + NV_WRITE(NV10_PGRAPH_CTX_USER, 0x0); + NV_WRITE(NV04_PFIFO_DELAY_0, 0xff /* retrycount*/ ); + if (dev_priv->card_type >= NV_40) + NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x00002001); + else + NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10110000); + } else { + NV_WRITE(NV04_PGRAPH_CTX_USER, 0x0); + NV_WRITE(NV04_PFIFO_DELAY_0, 0xff /* retrycount*/ ); + NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10110000); + } NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, 0x001fffff); NV_WRITE(NV03_PFIFO_CACHES, 0x00000001); - return 0; } diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index 542e7eca..966600cf 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -64,11 +64,7 @@ # define NV_PGRAPH_INTR_CONTEXT_SWITCH (1<<12) # define NV_PGRAPH_INTR_BUFFER_NOTIFY (1<<16) # define NV_PGRAPH_INTR_ERROR (1<<20) -#define NV03_PGRAPH_CTX_CONTROL 0x00400144 -#define NV40_PGRAPH_UNK220 0x00400220 -# define NV40_PGRAPH_UNK220_FB_INSTANCE 0xFFFFFFFF -#define NV03_PGRAPH_CTX_USER 0x00400194 -#define NV04_PGRAPH_CTX_USER 0x00400174 +#define NV10_PGRAPH_CTX_CONTROL 0x00400144 #define NV10_PGRAPH_CTX_USER 0x00400148 #define NV10_PGRAPH_CTX_SWITCH1 0x0040014C #define NV10_PGRAPH_CTX_SWITCH2 0x00400150 @@ -80,14 +76,20 @@ #define NV04_PGRAPH_CTX_SWITCH2 0x00400164 #define NV04_PGRAPH_CTX_SWITCH3 0x00400168 #define NV04_PGRAPH_CTX_SWITCH4 0x0040016C +#define NV04_PGRAPH_CTX_CONTROL 0x00400170 +#define NV04_PGRAPH_CTX_USER 0x00400174 #define NV04_PGRAPH_CTX_CACHE1 0x00400180 #define NV10_PGRAPH_CTX_CACHE2 0x00400180 +#define NV03_PGRAPH_CTX_CONTROL 0x00400190 +#define NV03_PGRAPH_CTX_USER 0x00400194 #define NV04_PGRAPH_CTX_CACHE2 0x004001A0 #define NV10_PGRAPH_CTX_CACHE3 0x004001A0 #define NV04_PGRAPH_CTX_CACHE3 0x004001C0 #define NV10_PGRAPH_CTX_CACHE4 0x004001C0 #define NV04_PGRAPH_CTX_CACHE4 0x004001E0 #define NV10_PGRAPH_CTX_CACHE5 0x004001E0 +#define NV40_PGRAPH_UNK220 0x00400220 +# define NV40_PGRAPH_UNK220_FB_INSTANCE 0xFFFFFFFF #define NV03_PGRAPH_ABS_X_RAM 0x00400400 #define NV03_PGRAPH_ABS_Y_RAM 0x00400480 #define NV03_PGRAPH_X_MISC 0x00400500 diff --git a/shared-core/nv04_graph.c b/shared-core/nv04_graph.c index d7d78001..830d673e 100644 --- a/shared-core/nv04_graph.c +++ b/shared-core/nv04_graph.c @@ -29,7 +29,7 @@ struct reg_interval { - int reg; + uint32_t reg; int number; } nv04_graph_ctx_regs [] = { {NV04_PGRAPH_CTX_SWITCH1, 1}, @@ -160,12 +160,10 @@ void nouveau_nv04_context_switch(drm_device_t *dev) DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel); + NV_WRITE(NV03_PFIFO_CACHES, 0x0); + NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0); + NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x0); NV_WRITE(NV04_PGRAPH_FIFO,0x0); -#if 0 - NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000); - NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000000); - NV_WRITE(NV_PFIFO_CACHES, 0x00000000); -#endif // save PGRAPH context index=0; @@ -178,8 +176,8 @@ void nouveau_nv04_context_switch(drm_device_t *dev) nouveau_wait_for_idle(dev); - NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10000000); - NV_WRITE(NV04_PGRAPH_CTX_USER, (NV_READ(NV04_PGRAPH_CTX_USER) & 0xffffff) | (0x1f << 24)); + NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10000000); + NV_WRITE(NV04_PGRAPH_CTX_USER, (NV_READ(NV04_PGRAPH_CTX_USER) & 0xffffff) | (0x0f << 24)); nouveau_wait_for_idle(dev); // restore PGRAPH context @@ -195,15 +193,14 @@ void nouveau_nv04_context_switch(drm_device_t *dev) nouveau_wait_for_idle(dev); #endif - NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10010100); + NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10010100); NV_WRITE(NV04_PGRAPH_CTX_USER, channel << 24); NV_WRITE(NV04_PGRAPH_FFINTFC_ST2, NV_READ(NV04_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); -#if 0 - NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001); - NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001); - NV_WRITE(NV_PFIFO_CACHES, 0x00000001); -#endif + NV_WRITE(NV04_PGRAPH_FIFO,0x0); + NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0); + NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x1); + NV_WRITE(NV03_PFIFO_CACHES, 0x1); NV_WRITE(NV04_PGRAPH_FIFO,0x1); } @@ -231,7 +228,7 @@ int nv04_graph_init(drm_device_t *dev) { for ( i = 0 ; i<sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++) sum+=nv04_graph_ctx_regs[i].number; if ( sum*4>sizeof(dev_priv->fifos[0].pgraph_ctx) ) - DRM_ERROR(); + DRM_ERROR("pgraph_ctx too small\n"); return 0; } |