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-rw-r--r--intel/intel_chipset.h53
1 files changed, 27 insertions, 26 deletions
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 5aea3f2b..3350defc 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -90,40 +90,40 @@
#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
#define PCI_CHIP_HASWELL_GT2 0x0412
-#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422
+#define PCI_CHIP_HASWELL_GT3 0x0422
#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
#define PCI_CHIP_HASWELL_M_GT2 0x0416
-#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426
+#define PCI_CHIP_HASWELL_M_GT3 0x0426
#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
#define PCI_CHIP_HASWELL_S_GT2 0x041A
-#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A
+#define PCI_CHIP_HASWELL_S_GT3 0x042A
#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
-#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22
+#define PCI_CHIP_HASWELL_SDV_GT3 0x0C22
#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
-#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
+#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26
#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
-#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
+#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A
#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
-#define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22
+#define PCI_CHIP_HASWELL_ULT_GT3 0x0A22
#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
-#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
+#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26
#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
-#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
+#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
#define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
#define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
-#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D22
+#define PCI_CHIP_HASWELL_CRW_GT3 0x0D22
#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */
#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
-#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26
+#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26
#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
-#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A
+#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
#define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */
#define PCI_CHIP_VALLEYVIEW_1 0x0f31
@@ -230,22 +230,23 @@
(devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
(devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
(devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
- (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
- (devid) == PCI_CHIP_HASWELL_GT2_PLUS || \
- (devid) == PCI_CHIP_HASWELL_M_GT2_PLUS || \
- (devid) == PCI_CHIP_HASWELL_S_GT2_PLUS || \
- (devid) == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \
- (devid) == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \
- (devid) == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \
- (devid) == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \
- (devid) == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \
- (devid) == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \
- (devid) == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \
- (devid) == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \
- (devid) == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)
+ (devid) == PCI_CHIP_HASWELL_CRW_S_GT2)
+#define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_M_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_S_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_S_GT3)
#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
- IS_HSW_GT2(devid))
+ IS_HSW_GT2(devid) || \
+ IS_HSW_GT3(devid))
#define IS_9XX(dev) (IS_GEN3(dev) || \
IS_GEN4(dev) || \