diff options
| -rw-r--r-- | linux-core/Makefile.kernel | 2 | ||||
| l--------- | linux-core/nv10_graph.c | 1 | ||||
| -rw-r--r-- | shared-core/nouveau_drv.h | 9 | ||||
| -rw-r--r-- | shared-core/nouveau_fifo.c | 6 | ||||
| -rw-r--r-- | shared-core/nouveau_irq.c | 31 | ||||
| -rw-r--r-- | shared-core/nouveau_state.c | 2 | ||||
| -rw-r--r-- | shared-core/nv10_graph.c | 594 |
7 files changed, 608 insertions, 37 deletions
diff --git a/linux-core/Makefile.kernel b/linux-core/Makefile.kernel index 30df582c..1bfffa03 100644 --- a/linux-core/Makefile.kernel +++ b/linux-core/Makefile.kernel @@ -22,7 +22,7 @@ i830-objs := i830_drv.o i830_dma.o i830_irq.o i915-objs := i915_drv.o i915_dma.o i915_irq.o i915_mem.o i915_fence.o \ i915_buffer.o nouveau-objs := nouveau_drv.o nouveau_state.o nouveau_fifo.o nouveau_mem.o \ - nouveau_object.o nouveau_irq.o nv30_graph.o nv40_graph.o + nouveau_object.o nouveau_irq.o nv10_graph.o nv30_graph.o nv40_graph.o radeon-objs := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o radeon_irq.o r300_cmdbuf.o sis-objs := sis_drv.o sis_mm.o ffb-objs := ffb_drv.o ffb_context.o diff --git a/linux-core/nv10_graph.c b/linux-core/nv10_graph.c new file mode 120000 index 00000000..0d5a0eb4 --- /dev/null +++ b/linux-core/nv10_graph.c @@ -0,0 +1 @@ +../shared-core/nv10_graph.c
\ No newline at end of file diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 219ba123..9466cdcd 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -90,8 +90,8 @@ struct nouveau_fifo /* objects belonging to this fifo */ struct nouveau_object *objs; - /* XXX move this in PGRAPH struct */ - uint32_t pgraph_ctx_user; + /* XXX dynamic alloc ? */ + uint32_t nv10_pgraph_ctx [340]; }; struct nouveau_config { @@ -202,6 +202,11 @@ extern void nouveau_irq_preinstall(drm_device_t*); extern void nouveau_irq_postinstall(drm_device_t*); extern void nouveau_irq_uninstall(drm_device_t*); +/* nv10_graph.c */ +extern void nouveau_nv10_context_switch(drm_device_t *dev); +extern int nv10_graph_init(drm_device_t *dev); +extern int nv10_graph_context_create(drm_device_t *dev, int channel); + /* nv30_graph.c */ extern int nv30_graph_init(drm_device_t *dev); extern int nv30_graph_context_create(drm_device_t *dev, int channel); diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 98a1344e..cb94afc5 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -538,7 +538,6 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init, init->channel = i; init->put_base = 0; dev_priv->cur_fifo = init->channel; - dev_priv->fifos[i].pgraph_ctx_user = i << 24; nouveau_wait_for_idle(dev); @@ -551,8 +550,9 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init, /* Construct inital RAMFC for new channel */ if (dev_priv->card_type < NV_10) { nouveau_nv04_context_init(dev, init); - } else if (dev_priv->card_type < NV_30) { - nouveau_nv10_context_init(dev, init); + } else if (dev_priv->card_type < NV_30) { + nv10_graph_context_create(dev, init->channel); + nouveau_nv10_context_init(dev, init); } else if (dev_priv->card_type < NV_40) { ret = nv30_graph_context_create(dev, init->channel); if (ret) { diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index 7a31fb0b..638b094b 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -237,37 +237,6 @@ static void nouveau_nv04_context_switch(drm_device_t *dev) } -static void nouveau_nv10_context_switch(drm_device_t *dev) -{ - drm_nouveau_private_t *dev_priv = dev->dev_private; - int channel, channel_old; - - channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1); - channel_old = (NV_READ(NV_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); - - DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel); - - NV_WRITE(NV_PGRAPH_FIFO,0x0); - NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000); - NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000000); - NV_WRITE(NV_PFIFO_CACHES, 0x00000000); - - dev_priv->fifos[channel_old].pgraph_ctx_user = NV_READ(NV_PGRAPH_CTX_USER); - //XXX save PGRAPH context - NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10000000); - NV_WRITE(NV_PGRAPH_CTX_USER, dev_priv->fifos[channel].pgraph_ctx_user); - //XXX restore PGRAPH context - printk("ctx_user %x %x\n", dev_priv->fifos[channel_old].pgraph_ctx_user, dev_priv->fifos[channel].pgraph_ctx_user); - - NV_WRITE(NV_PGRAPH_FFINTFC_ST2, NV_READ(NV_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); - NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10010100); - - NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001); - NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001); - NV_WRITE(NV_PFIFO_CACHES, 0x00000001); - NV_WRITE(NV_PGRAPH_FIFO,0x1); -} - static void nouveau_pgraph_irq_handler(drm_device_t *dev) { uint32_t status; diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index 1e0587f6..6448512c 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -96,6 +96,8 @@ int nouveau_firstopen(struct drm_device *dev) /* FIXME: doesn't belong here, and have no idea what it's for.. */ if (dev_priv->card_type >= NV_40) nv40_graph_init(dev); + else if (dev_priv->card_type == NV_10) + nv10_graph_init(dev); return 0; } diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c new file mode 100644 index 00000000..ccbb34de --- /dev/null +++ b/shared-core/nv10_graph.c @@ -0,0 +1,594 @@ +/* + * Copyright 2007 Matthieu CASTET <castet.matthieu@free.fr> + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "drmP.h" +#include "drm.h" +#include "nouveau_drm.h" +#include "nouveau_drv.h" + + +static void nv10_praph_pipe(drm_device_t *dev) { + drm_nouveau_private_t *dev_priv = dev->dev_private; + int i; + + nouveau_wait_for_idle(dev); + /* XXX check haiku comments */ + NV_WRITE(NV_PGRAPH_XFMODE0, 0x10000000); + NV_WRITE(NV_PGRAPH_XFMODE1, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x000064c0); + for (i = 0; i < 4; i++) + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); + for (i = 0; i < 4; i++) + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + + NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006ab0); + + for (i = 0; i < 3; i++) + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); + + NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006a80); + for (i = 0; i < 3; i++) + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + + NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000040); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000008); + + NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000200); + for (i = 0; i < 48; i++) + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + + nouveau_wait_for_idle(dev); + + NV_WRITE(NV_PGRAPH_XFMODE0, 0x00000000); + NV_WRITE(NV_PGRAPH_XFMODE1, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006400); + for (i = 0; i < 211; i++) + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); + + NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006800); + for (i = 0; i < 162; i++) + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); + for (i = 0; i < 25; i++) + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + + NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006c00); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0xbf800000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00007000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); + for (i = 0; i < 35; i++) + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + + + NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00007400); + for (i = 0; i < 48; i++) + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + + NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00007800); + for (i = 0; i < 48; i++) + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + + NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00004400); + for (i = 0; i < 32; i++) + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + + NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000000); + for (i = 0; i < 16; i++) + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + + NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000040); + for (i = 0; i < 4; i++) + NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + + nouveau_wait_for_idle(dev); +} + +/* TODO replace address with name + use loops */ +static int nv10_graph_ctx_regs [] = { +NV_PGRAPH_XY_LOGIC_MISC0, +NV_PGRAPH_DEBUG_4, +0x004006b0, + +NV_PGRAPH_CTX_SWITCH1, +NV_PGRAPH_CTX_SWITCH2, +NV_PGRAPH_CTX_SWITCH3, +NV_PGRAPH_CTX_SWITCH4, +NV_PGRAPH_CTX_SWITCH5, +0x00400160, +0x00400180, +0x004001a0, +0x004001c0, +0x004001e0, +0x00400164, +0x00400184, +0x004001a4, +0x004001c4, +0x004001e4, +0x00400168, +0x00400188, +0x004001a8, +0x004001c8, +0x004001e8, +0x0040016c, +0x0040018c, +0x004001ac, +0x004001cc, +0x004001ec, +0x00400170, +0x00400190, +0x004001b0, +0x004001d0, +0x004001f0, +0x00400174, +0x00400194, +0x004001b4, +0x004001d4, +0x004001f4, +0x00400178, +0x00400198, +0x004001b8, +0x004001d8, +0x004001f8, +0x0040017c, +0x0040019c, +0x004001bc, +0x004001dc, +0x004001fc, +NV_PGRAPH_CTX_USER, +NV_PGRAPH_DMA_START_0, +NV_PGRAPH_DMA_START_1, +NV_PGRAPH_DMA_LENGTH, +NV_PGRAPH_DMA_MISC, +NV_PGRAPH_DMA_PITCH, +NV_PGRAPH_BOFFSET0, +NV_PGRAPH_BBASE0, +NV_PGRAPH_BLIMIT0, +NV_PGRAPH_BOFFSET1, +NV_PGRAPH_BBASE1, +NV_PGRAPH_BLIMIT1, +NV_PGRAPH_BOFFSET2, +NV_PGRAPH_BBASE2, +NV_PGRAPH_BLIMIT2, +NV_PGRAPH_BOFFSET3, +NV_PGRAPH_BBASE3, +NV_PGRAPH_BLIMIT3, +NV_PGRAPH_BOFFSET4, +NV_PGRAPH_BBASE4, +NV_PGRAPH_BLIMIT4, +NV_PGRAPH_BOFFSET5, +NV_PGRAPH_BBASE5, +NV_PGRAPH_BLIMIT5, +NV_PGRAPH_BPITCH0, +NV_PGRAPH_BPITCH1, +NV_PGRAPH_BPITCH2, +NV_PGRAPH_BPITCH3, +NV_PGRAPH_BPITCH4, +NV_PGRAPH_SURFACE, +NV_PGRAPH_STATE, +NV_PGRAPH_BSWIZZLE2, +NV_PGRAPH_BSWIZZLE5, +NV_PGRAPH_BPIXEL, +NV_PGRAPH_NOTIFY, +NV_PGRAPH_PATT_COLOR0, +NV_PGRAPH_PATT_COLOR1, +0x00400900, +0x00400904, +0x00400908, +0x0040090c, +0x00400910, +0x00400914, +0x00400918, +0x0040091c, +0x00400920, +0x00400924, +0x00400928, +0x0040092c, +0x00400930, +0x00400934, +0x00400938, +0x0040093c, +0x00400940, +0x00400944, +0x00400948, +0x0040094c, +0x00400950, +0x00400954, +0x00400958, +0x0040095c, +0x00400960, +0x00400964, +0x00400968, +0x0040096c, +0x00400970, +0x00400974, +0x00400978, +0x0040097c, +0x00400980, +0x00400984, +0x00400988, +0x0040098c, +0x00400990, +0x00400994, +0x00400998, +0x0040099c, +0x004009a0, +0x004009a4, +0x004009a8, +0x004009ac, +0x004009b0, +0x004009b4, +0x004009b8, +0x004009bc, +0x004009c0, +0x004009c4, +0x004009c8, +0x004009cc, +0x004009d0, +0x004009d4, +0x004009d8, +0x004009dc, +0x004009e0, +0x004009e4, +0x004009e8, +0x004009ec, +0x004009f0, +0x004009f4, +0x004009f8, +0x004009fc, +0x00400808, +0x0040080c, +NV_PGRAPH_PATTERN_SHAPE, +NV_PGRAPH_MONO_COLOR0, +NV_PGRAPH_ROP3, +NV_PGRAPH_CHROMA, +NV_PGRAPH_BETA_AND, +NV_PGRAPH_BETA_PREMULT, +0x00400e70, +0x00400e74, +0x00400e78, +0x00400e7c, +0x00400e80, +0x00400e84, +0x00400e88, +0x00400e8c, +0x00400ea0, +0x00400ea4, +0x00400ea8, +0x00400eac, +0x00400eb0, +0x00400eb4, +0x00400eb8, +0x00400ebc, +0x00400ec0, +0x00400ec4, +0x00400ec8, +0x00400ecc, +0x00400ed0, +0x00400ed4, +0x00400ed8, +0x00400edc, +0x00400ee0, +0x00400a00, +0x00400a04, +0x00400e90, +0x00400e94, +0x00400e98, +0x00400e9c, +0x00400f00, +0x00400f20, +0x00400f04, +0x00400f24, +0x00400f08, +0x00400f28, +0x00400f0c, +0x00400f2c, +0x00400f10, +0x00400f30, +0x00400f14, +0x00400f34, +0x00400f18, +0x00400f38, +0x00400f1c, +0x00400f3c, +NV_PGRAPH_XFMODE0, +NV_PGRAPH_XFMODE1, +NV_PGRAPH_GLOBALSTATE0, +NV_PGRAPH_GLOBALSTATE1, +NV_PGRAPH_STORED_FMT, +NV_PGRAPH_SOURCE_COLOR, +0x00400400, +0x00400480, +0x00400404, +0x00400484, +0x00400408, +0x00400488, +0x0040040c, +0x0040048c, +0x00400410, +0x00400490, +0x00400414, +0x00400494, +0x00400418, +0x00400498, +0x0040041c, +0x0040049c, +0x00400420, +0x004004a0, +0x00400424, +0x004004a4, +0x00400428, +0x004004a8, +0x0040042c, +0x004004ac, +0x00400430, +0x004004b0, +0x00400434, +0x004004b4, +0x00400438, +0x004004b8, +0x0040043c, +0x004004bc, +0x00400440, +0x004004c0, +0x00400444, +0x004004c4, +0x00400448, +0x004004c8, +0x0040044c, +0x004004cc, +0x00400450, +0x004004d0, +0x00400454, +0x004004d4, +0x00400458, +0x004004d8, +0x0040045c, +0x004004dc, +0x00400460, +0x004004e0, +0x00400464, +0x004004e4, +0x00400468, +0x004004e8, +0x0040046c, +0x004004ec, +0x00400470, +0x004004f0, +0x00400474, +0x004004f4, +0x00400478, +0x004004f8, +0x0040047c, +0x004004fc, +NV_PGRAPH_ABS_UCLIP_XMIN, +NV_PGRAPH_ABS_UCLIP_XMAX, +NV_PGRAPH_ABS_UCLIP_YMIN, +NV_PGRAPH_ABS_UCLIP_YMAX, +0x00400550, +0x00400558, +0x00400554, +0x0040055c, +NV_PGRAPH_ABS_UCLIPA_XMIN, +NV_PGRAPH_ABS_UCLIPA_XMAX, +NV_PGRAPH_ABS_UCLIPA_YMIN, +NV_PGRAPH_ABS_UCLIPA_YMAX, +NV_PGRAPH_ABS_ICLIP_XMAX, +NV_PGRAPH_ABS_ICLIP_YMAX, +NV_PGRAPH_XY_LOGIC_MISC1, +NV_PGRAPH_XY_LOGIC_MISC2, +NV_PGRAPH_XY_LOGIC_MISC3, +NV_PGRAPH_CLIPX_0, +NV_PGRAPH_CLIPX_1, +NV_PGRAPH_CLIPY_0, +NV_PGRAPH_CLIPY_1, +0x00400e40, +0x00400e44, +0x00400e48, +0x00400e4c, +0x00400e50, +0x00400e54, +0x00400e58, +0x00400e5c, +0x00400e60, +0x00400e64, +0x00400e68, +0x00400e6c, +0x00400e00, +0x00400e04, +0x00400e08, +0x00400e0c, +0x00400e10, +0x00400e14, +0x00400e18, +0x00400e1c, +0x00400e20, +0x00400e24, +0x00400e28, +0x00400e2c, +0x00400e30, +0x00400e34, +0x00400e38, +0x00400e3c, +NV_PGRAPH_PASSTHRU_0, +NV_PGRAPH_PASSTHRU_1, +NV_PGRAPH_PASSTHRU_2, +NV_PGRAPH_DIMX_TEXTURE, +NV_PGRAPH_WDIMX_TEXTURE, +NV_PGRAPH_DVD_COLORFMT, +NV_PGRAPH_SCALED_FORMAT, +NV_PGRAPH_MISC24_0, +NV_PGRAPH_MISC24_1, +NV_PGRAPH_MISC24_2, +NV_PGRAPH_X_MISC, +NV_PGRAPH_Y_MISC, +NV_PGRAPH_VALID1, +NV_PGRAPH_VALID2, +0 +}; + +void nouveau_nv10_context_switch(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + int channel, channel_old, i; + + channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1); + channel_old = (NV_READ(NV_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); + + DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel); + + NV_WRITE(NV_PGRAPH_FIFO,0x0); +#if 0 + NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000); + NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000000); + NV_WRITE(NV_PFIFO_CACHES, 0x00000000); +#endif + + // save PGRAPH context + for (i = 0; nv10_graph_ctx_regs[i]; i++) + dev_priv->fifos[channel_old].nv10_pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); + + nouveau_wait_for_idle(dev); + + NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10000000); + NV_WRITE(NV_PGRAPH_CTX_USER, (NV_READ(NV_PGRAPH_CTX_USER) & 0xffffff) | (0x1f << 24)); + + nouveau_wait_for_idle(dev); + // restore PGRAPH context + //XXX not working yet +#if 0 + for (i = 0; nv10_graph_ctx_regs[i]; i++) + NV_WRITE(nv10_graph_ctx_regs[i], dev_priv->fifos[channel].nv10_pgraph_ctx[i]); + nouveau_wait_for_idle(dev); +#endif + + NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10010100); + NV_WRITE(NV_PGRAPH_CTX_USER, channel << 24); + NV_WRITE(NV_PGRAPH_FFINTFC_ST2, NV_READ(NV_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); + +#if 0 + NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001); + NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001); + NV_WRITE(NV_PFIFO_CACHES, 0x00000001); +#endif + NV_WRITE(NV_PGRAPH_FIFO,0x1); +} + +int nv10_graph_context_create(drm_device_t *dev, int channel) { + drm_nouveau_private_t *dev_priv = dev->dev_private; + DRM_DEBUG("nv10_graph_context_create %d\n", channel); + + memset(dev_priv->fifos[channel].nv10_pgraph_ctx, 0, sizeof(dev_priv->fifos[channel].nv10_pgraph_ctx)); + + //dev_priv->fifos[channel].pgraph_ctx_user = channel << 24; + dev_priv->fifos[channel].nv10_pgraph_ctx[0] = 0x0001ffff; + /* is it really needed ??? */ + dev_priv->fifos[channel].nv10_pgraph_ctx[1] = NV_READ(NV_PGRAPH_DEBUG_4); + dev_priv->fifos[channel].nv10_pgraph_ctx[2] = NV_READ(0x004006b0); + return 0; +} + + +int nv10_graph_init(drm_device_t *dev) { + //XXX should be call at each fifo init + nv10_praph_pipe(dev); + return 0; +} |