diff options
| -rw-r--r-- | shared-core/r300_reg.h | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/shared-core/r300_reg.h b/shared-core/r300_reg.h index a85a7d48..1f65f9a7 100644 --- a/shared-core/r300_reg.h +++ b/shared-core/r300_reg.h @@ -325,7 +325,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * Most likely this is used to ignore rest of the program in cases * where group of verts arent visible. For some reason this "section" * is sometimes accepted other instruction that have no relationship with - *position calculations. + *position calculations. */ #define R300_VAP_PVS_CNTL_1 0x22D0 # define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0 @@ -497,6 +497,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. /* Zero to flush caches. */ #define R300_TX_CNTL 0x4100 +#define R300_TX_FLUSH 0x0 /* The upper enable bits are guessed, based on fglrx reported limits. */ #define R300_TX_ENABLE 0x4104 @@ -565,12 +566,13 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #define R300_RE_FOG_SCALE 0x4294 #define R300_RE_FOG_START 0x4298 -/* Not sure why there are duplicate of factor and constant values. - * My best guess so far is that there are seperate zbiases for test and write. +/* Not sure why there are duplicate of factor and constant values. + * My best guess so far is that there are seperate zbiases for test and write. * Ordering might be wrong. * Some of the tests indicate that fgl has a fallback implementation of zbias * via pixel shaders. */ +#define R300_RE_ZBIAS_CNTL 0x42A0 /* GUESS */ #define R300_RE_ZBIAS_T_FACTOR 0x42A4 #define R300_RE_ZBIAS_T_CONSTANT 0x42A8 #define R300_RE_ZBIAS_W_FACTOR 0x42AC @@ -907,7 +909,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. /* 32 bit chroma key */ #define R300_TX_CHROMA_KEY_0 0x4580 /* ff00ff00 == { 0, 1.0, 0, 1.0 } */ -#define R300_TX_BORDER_COLOR_0 0x45C0 +#define R300_TX_BORDER_COLOR_0 0x45C0 /* END: Texture specification */ @@ -997,6 +999,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_FPITX_OP_KIL 2 # define R300_FPITX_OP_TXP 3 # define R300_FPITX_OP_TXB 4 +# define R300_FPITX_OPCODE_MASK (7 << 15) /* ALU * The ALU instructions register blocks are enumerated according to the order @@ -1045,7 +1048,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * WRT swizzling. If, for example, you want to load an R component into an * Alpha operand, this R component is taken from a *color* source, not from * an alpha source. The corresponding register doesn't even have to appear in - * the alpha sources list. (I hope this alll makes sense to you) + * the alpha sources list. (I hope this all makes sense to you) * * Destination selection * The destination register index is in FPI1 (color) and FPI3 (alpha) @@ -1072,6 +1075,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_FPI1_SRC2C_SHIFT 12 # define R300_FPI1_SRC2C_MASK (31 << 12) # define R300_FPI1_SRC2C_CONST (1 << 17) +# define R300_FPI1_SRC_MASK 0x0003ffff # define R300_FPI1_DSTC_SHIFT 18 # define R300_FPI1_DSTC_MASK (31 << 18) # define R300_FPI1_DSTC_REG_MASK_SHIFT 23 @@ -1093,6 +1097,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_FPI3_SRC2A_SHIFT 12 # define R300_FPI3_SRC2A_MASK (31 << 12) # define R300_FPI3_SRC2A_CONST (1 << 17) +# define R300_FPI3_SRC_MASK 0x0003ffff # define R300_FPI3_DSTA_SHIFT 18 # define R300_FPI3_DSTA_MASK (31 << 18) # define R300_FPI3_DSTA_REG (1 << 23) |