summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--linux-core/i915_drv.c8
-rw-r--r--shared-core/i915_drv.h4
2 files changed, 6 insertions, 6 deletions
diff --git a/linux-core/i915_drv.c b/linux-core/i915_drv.c
index 5a6f0adc..91c2da23 100644
--- a/linux-core/i915_drv.c
+++ b/linux-core/i915_drv.c
@@ -172,7 +172,7 @@ static void i915_save_vga(struct drm_device *dev)
i915_write_indexed(cr_index, cr_data, 0x11,
i915_read_indexed(cr_index, cr_data, 0x11) &
(~0x80));
- for (i = 0; i < 0x24; i++)
+ for (i = 0; i <= 0x24; i++)
dev_priv->saveCR[i] =
i915_read_indexed(cr_index, cr_data, i);
/* Make sure we don't turn off CR group 0 writes */
@@ -181,7 +181,7 @@ static void i915_save_vga(struct drm_device *dev)
/* Attribute controller registers */
inb(st01);
dev_priv->saveAR_INDEX = inb(VGA_AR_INDEX);
- for (i = 0; i < 20; i++)
+ for (i = 0; i <= 0x14; i++)
dev_priv->saveAR[i] = i915_read_ar(st01, i, 0);
inb(st01);
outb(dev_priv->saveAR_INDEX, VGA_AR_INDEX);
@@ -231,7 +231,7 @@ static void i915_restore_vga(struct drm_device *dev)
/* CRT controller regs */
/* Enable CR group 0 writes */
i915_write_indexed(cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
- for (i = 0; i < 0x24; i++)
+ for (i = 0; i <= 0x24; i++)
i915_write_indexed(cr_index, cr_data, i, dev_priv->saveCR[i]);
/* Graphics controller regs */
@@ -248,7 +248,7 @@ static void i915_restore_vga(struct drm_device *dev)
/* Attribute controller registers */
inb(st01); /* switch back to index mode */
- for (i = 0; i < 20; i++)
+ for (i = 0; i <= 0x14; i++)
i915_write_ar(st01, i, dev_priv->saveAR[i], 0);
inb(st01); /* switch back to index mode */
outb(dev_priv->saveAR_INDEX | 0x20, VGA_AR_INDEX);
diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h
index 412a2594..aad74b1c 100644
--- a/shared-core/i915_drv.h
+++ b/shared-core/i915_drv.h
@@ -237,10 +237,10 @@ typedef struct drm_i915_private {
u8 saveSR[8];
u8 saveGR[25];
u8 saveAR_INDEX;
- u8 saveAR[20];
+ u8 saveAR[21];
u8 saveDACMASK;
u8 saveDACDATA[256*3]; /* 256 3-byte colors */
- u8 saveCR[36];
+ u8 saveCR[37];
} drm_i915_private_t;
enum intel_chip_family {