diff options
| -rw-r--r-- | shared-core/radeon_drm.h | 3 | ||||
| -rw-r--r-- | shared-core/radeon_drv.h | 1 | ||||
| -rw-r--r-- | shared-core/radeon_state.c | 4 | ||||
| -rw-r--r-- | shared/radeon.h | 4 | ||||
| -rw-r--r-- | shared/radeon_drm.h | 3 | ||||
| -rw-r--r-- | shared/radeon_drv.h | 1 | ||||
| -rw-r--r-- | shared/radeon_state.c | 4 |
7 files changed, 15 insertions, 5 deletions
diff --git a/shared-core/radeon_drm.h b/shared-core/radeon_drm.h index c60c09fd..735e04ef 100644 --- a/shared-core/radeon_drm.h +++ b/shared-core/radeon_drm.h @@ -144,7 +144,8 @@ #define RADEON_EMIT_PP_TEX_SIZE_0 73 #define RADEON_EMIT_PP_TEX_SIZE_1 74 #define RADEON_EMIT_PP_TEX_SIZE_2 75 -#define RADEON_MAX_STATE_PACKETS 76 +#define R200_EMIT_RB3D_BLENDCOLOR 76 +#define RADEON_MAX_STATE_PACKETS 77 /* Commands understood by cmd_buffer ioctl. More can be added but diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index afa516e8..45eafd05 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -690,6 +690,7 @@ extern void radeon_do_release(drm_device_t *dev); #define R200_SE_VTX_FMT_1 0x208c #define R200_RE_CNTL 0x1c50 +#define R200_RB3D_BLENDCOLOR 0x3218 /* Constants */ #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c index fca72827..876c91d4 100644 --- a/shared-core/radeon_state.c +++ b/shared-core/radeon_state.c @@ -201,6 +201,7 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_ case RADEON_EMIT_PP_TEX_SIZE_0: case RADEON_EMIT_PP_TEX_SIZE_1: case RADEON_EMIT_PP_TEX_SIZE_2: + case R200_EMIT_RB3D_BLENDCOLOR: /* These packets don't contain memory offsets */ break; @@ -562,7 +563,8 @@ static struct { { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" }, { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" }, { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" }, - { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_1" }, + { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" }, + { R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" }, }; diff --git a/shared/radeon.h b/shared/radeon.h index 4219384f..c9bdaee5 100644 --- a/shared/radeon.h +++ b/shared/radeon.h @@ -51,7 +51,7 @@ #define DRIVER_DATE "20020828" #define DRIVER_MAJOR 1 -#define DRIVER_MINOR 10 +#define DRIVER_MINOR 11 #define DRIVER_PATCHLEVEL 0 /* Interface history: @@ -84,6 +84,8 @@ * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which * clients use to tell the DRM where they think the framebuffer is * located in the card's address space + * 1.11 Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color + * and GL_EXT_blend_[func|equation]_separate on r200 */ #define DRIVER_IOCTLS \ [DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { radeon_cp_buffers, 1, 0 }, \ diff --git a/shared/radeon_drm.h b/shared/radeon_drm.h index c60c09fd..735e04ef 100644 --- a/shared/radeon_drm.h +++ b/shared/radeon_drm.h @@ -144,7 +144,8 @@ #define RADEON_EMIT_PP_TEX_SIZE_0 73 #define RADEON_EMIT_PP_TEX_SIZE_1 74 #define RADEON_EMIT_PP_TEX_SIZE_2 75 -#define RADEON_MAX_STATE_PACKETS 76 +#define R200_EMIT_RB3D_BLENDCOLOR 76 +#define RADEON_MAX_STATE_PACKETS 77 /* Commands understood by cmd_buffer ioctl. More can be added but diff --git a/shared/radeon_drv.h b/shared/radeon_drv.h index afa516e8..45eafd05 100644 --- a/shared/radeon_drv.h +++ b/shared/radeon_drv.h @@ -690,6 +690,7 @@ extern void radeon_do_release(drm_device_t *dev); #define R200_SE_VTX_FMT_1 0x208c #define R200_RE_CNTL 0x1c50 +#define R200_RB3D_BLENDCOLOR 0x3218 /* Constants */ #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ diff --git a/shared/radeon_state.c b/shared/radeon_state.c index fca72827..876c91d4 100644 --- a/shared/radeon_state.c +++ b/shared/radeon_state.c @@ -201,6 +201,7 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_ case RADEON_EMIT_PP_TEX_SIZE_0: case RADEON_EMIT_PP_TEX_SIZE_1: case RADEON_EMIT_PP_TEX_SIZE_2: + case R200_EMIT_RB3D_BLENDCOLOR: /* These packets don't contain memory offsets */ break; @@ -562,7 +563,8 @@ static struct { { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" }, { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" }, { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" }, - { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_1" }, + { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" }, + { R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" }, }; |