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authorMichel Dänzer <michel.daenzer@amd.com>2013-01-17 19:03:42 +0100
committerMichel Dänzer <michel@daenzer.net>2013-01-18 20:24:35 +0100
commit303ca37e722e68900cb7eb43ddbef8069b0c711b (patch)
tree0f892f7f7fbfc4d4b467b36c3edc0f9ea5079ba1 /xf86drmHash.c
parent08cb5c1d0245f6bfc1dd4d041eb418bc160c7b05 (diff)
radeon: Fix 1D tiling layout on SI.
Very similar to Evergreen, but slightly different rules for tile / slice alignment. Fortunately, these map quite naturally onto the previous fixes for linear aligned layout on SI. 2D tiling still needs more work here and possibly in the kernel. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Diffstat (limited to 'xf86drmHash.c')
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