diff options
author | Roland Scheidegger <rscheidegger_lists@hispeed.ch> | 2005-03-15 22:12:30 +0000 |
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committer | Roland Scheidegger <rscheidegger_lists@hispeed.ch> | 2005-03-15 22:12:30 +0000 |
commit | 34563921dd0b41d4ccf08374227e31d765b40353 (patch) | |
tree | 8923166e153a310096f278a5cdd743b347fcb584 /shared/radeon_state.c | |
parent | d2fd9200956a94cfd91a39e76994f326bdfc6ac0 (diff) |
add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear filtering on
r200
Diffstat (limited to 'shared/radeon_state.c')
-rw-r--r-- | shared/radeon_state.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/shared/radeon_state.c b/shared/radeon_state.c index a360b17c..0f7550bd 100644 --- a/shared/radeon_state.c +++ b/shared/radeon_state.c @@ -207,6 +207,7 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_ case RADEON_EMIT_PP_CUBIC_FACES_0: case RADEON_EMIT_PP_CUBIC_FACES_1: case RADEON_EMIT_PP_CUBIC_FACES_2: + case R200_EMIT_PP_TRI_PERF_CNTL: /* These packets don't contain memory offsets */ break; @@ -567,6 +568,7 @@ static struct { { RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, + { R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, }; |