Radeon IGP: clean up registers and magic numbers

2 files changed, 121 insertions, 96 deletions

diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c
index 89d2a241..14317f28 100644
--- a/shared-core/radeon_cp.c
+++ b/shared-core/radeon_cp.c
@@ -16171,9 +16171,9 @@ static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
 {
 	u32 ret;
-	RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f);
-	ret = RADEON_READ(RADEON_IGPGART_DATA);
-	RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f);
+	RADEON_WRITE(RS400_NB_MC_INDEX, addr & 0x7f);
+	ret = RADEON_READ(RS400_NB_MC_DATA);
+	RADEON_WRITE(RS400_NB_MC_INDEX, 0x7f);
 	return ret;
 }
 
@@ -16676,14 +16676,18 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 			 (long)dev_priv->gart_info.bus_addr,
 			 dev_priv->gart_size);
 
-		RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000);
-		RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1);
-		RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800);
-		RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR,
+		RADEON_WRITE_IGPGART(RS400_MC_MISC_CNTL, RS400_GART_INDEX_REG_EN);
+		RADEON_WRITE_IGPGART(RS400_AGP_ADDRESS_SPACE_SIZE, (RS400_GART_EN |
+								    RS400_VA_SIZE_32MB));
+		RADEON_WRITE_IGPGART(RS400_GART_FEATURE_ID, (RS400_HANG_EN |
+							     RS400_TLB_ENABLE |
+							     RS400_GTW_LAC_EN |
+							     RS400_1LEVEL_GART));
+		RADEON_WRITE_IGPGART(RS400_GART_BASE,
 				     dev_priv->gart_info.bus_addr);
 
-		temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39);
-		RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp);
+		temp = RADEON_READ_IGPGART(dev_priv, RS400_AGP_MODE_CNTL);
+		RADEON_WRITE_IGPGART(RS400_AGP_MODE_CNTL, temp);
 
 		RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
 		dev_priv->gart_size = 32*1024*1024;
@@ -16692,13 +16696,13 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 			       dev_priv->gart_size) & 0xffff0000) |
 			     (dev_priv->gart_vm_start >> 16)));
 
-		temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE);
-		RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp);
+		temp = RADEON_READ_IGPGART(dev_priv, RS400_AGP_ADDRESS_SPACE_SIZE);
+		RADEON_WRITE_IGPGART(RS400_AGP_ADDRESS_SPACE_SIZE, temp);
 
-		RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
-		RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
-		RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
-		RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
+		RADEON_READ_IGPGART(dev_priv, RS400_GART_CACHE_CNTRL);
+		RADEON_WRITE_IGPGART(RS400_GART_CACHE_CNTRL, RS400_GART_CACHE_INVALIDATE);
+		RADEON_READ_IGPGART(dev_priv, RS400_GART_CACHE_CNTRL);
+		RADEON_WRITE_IGPGART(RS400_GART_CACHE_CNTRL, 0);
        }
 }
 
@@ -16713,22 +16717,27 @@ static void radeon_set_rs690gart(drm_radeon_private_t * dev_priv, int on)
 			 (long)dev_priv->gart_info.bus_addr,
 			 dev_priv->gart_size);
 
-		temp = RS690_READ_MCIND(dev_priv, RS690_MC_MISC_CNTL);
-		RS690_WRITE_MCIND(RS690_MC_MISC_CNTL, 0x5000);
+		temp = RS690_READ_MCIND(dev_priv, RS400_MC_MISC_CNTL);
+		RS690_WRITE_MCIND(RS400_MC_MISC_CNTL, (RS400_GART_INDEX_REG_EN |
+						       RS690_BLOCK_GFX_D3_EN));
 
-		RS690_WRITE_MCIND(RS690_MC_AGP_SIZE,
-                  RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB);
-		
-		temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_FEATURE_ID);
-		RS690_WRITE_MCIND(RS690_MC_GART_FEATURE_ID, 0x42040800);
+		RS690_WRITE_MCIND(RS400_AGP_ADDRESS_SPACE_SIZE, (RS400_GART_EN |
+								 RS400_VA_SIZE_32MB));
+
+		temp = RS690_READ_MCIND(dev_priv, RS400_GART_FEATURE_ID);
+		RS690_WRITE_MCIND(RS400_GART_FEATURE_ID, (RS400_HANG_EN |
+							  RS400_TLB_ENABLE |
+							  RS400_GTW_LAC_EN |
+							  RS400_1LEVEL_GART));
 
 		temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 		temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
-		RS690_WRITE_MCIND(RS690_MC_GART_BASE, temp);
-		
-		temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_MODE_CONTROL);
-		RS690_WRITE_MCIND(RS690_MC_AGP_MODE_CONTROL, 0x01400000);
-		
+		RS690_WRITE_MCIND(RS400_GART_BASE, temp);
+
+		temp = RS690_READ_MCIND(dev_priv, RS400_AGP_MODE_CNTL);
+		RS690_WRITE_MCIND(RS400_AGP_MODE_CNTL, ((1 << RS400_REQ_TYPE_SNOOP_SHIFT) |
+							RS400_REQ_TYPE_SNOOP_DIS));
+
 		RS690_WRITE_MCIND(RS690_MC_AGP_BASE,
 				(unsigned int)dev_priv->gart_vm_start);
 
@@ -16739,37 +16748,34 @@ static void radeon_set_rs690gart(drm_radeon_private_t * dev_priv, int on)
 			0xffff0000) | (dev_priv->gart_vm_start >> 16));
 
 		RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, temp);
-		
-		temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_SIZE);
-    		RS690_WRITE_MCIND(RS690_MC_AGP_SIZE,
-                      RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB);
-
-    		do
-    		{
-        	    temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL);
-	            if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
-    		            RS690_MC_GART_CLEAR_DONE)
-            		break;
-        	    DRM_UDELAY(1);
-    		} while(1);
-
-	        RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL,
-        	                    RS690_MC_GART_CC_CLEAR);
-    		do
-    		{
-	            temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL);
-        	    if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
-                	    RS690_MC_GART_CLEAR_DONE)
-	                break;
-    		    DRM_UDELAY(1);
-	        } while(1);
-
-	        RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL,
-    		                    RS690_MC_GART_CC_NO_CHANGE);
-    }
-    else
-    {
-        RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, RS690_MC_GART_DIS);
+
+		temp = RS690_READ_MCIND(dev_priv, RS400_AGP_ADDRESS_SPACE_SIZE);
+		RS690_WRITE_MCIND(RS400_AGP_ADDRESS_SPACE_SIZE, (RS400_GART_EN |
+								 RS400_VA_SIZE_32MB));
+
+		/* ??? */
+		do {
+		    temp = RS690_READ_MCIND(dev_priv, RS400_GART_CACHE_CNTRL);
+		    if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
+			    RS690_MC_GART_CLEAR_DONE)
+			break;
+		    DRM_UDELAY(1);
+		} while(1);
+
+		RS690_WRITE_MCIND(RS400_GART_CACHE_CNTRL,
+				  RS400_GART_CACHE_INVALIDATE);
+		/* ??? */
+		do {
+		    temp = RS690_READ_MCIND(dev_priv, RS400_GART_CACHE_CNTRL);
+		    if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
+			    RS690_MC_GART_CLEAR_DONE)
+			break;
+		    DRM_UDELAY(1);
+		} while(1);
+
+		RS690_WRITE_MCIND(RS400_GART_CACHE_CNTRL, 0);
+    } else {
+	RS690_WRITE_MCIND(RS400_AGP_ADDRESS_SPACE_SIZE, 0);
     }
 }
 
diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index e8fb00df..639a1398 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -448,13 +448,13 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #define RADEON_PCIE_DATA                0x0034
 #define RADEON_PCIE_TX_GART_CNTL	0x10
 #	define RADEON_PCIE_TX_GART_EN		(1 << 0)
-#	define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
-#	define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO  (1<<1)
-#	define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD   (3<<1)
-#	define RADEON_PCIE_TX_GART_MODE_32_128_CACHE	(0<<3)
-#	define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE	(1<<3)
-#	define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN      (1<<5)
-#	define RADEON_PCIE_TX_GART_INVALIDATE_TLB	(1<<8)
+#	define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
+#	define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO  (1 << 1)
+#	define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD   (3 << 1)
+#	define RADEON_PCIE_TX_GART_MODE_32_128_CACHE	(0 << 3)
+#	define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE	(1 << 3)
+#	define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN      (1 << 5)
+#	define RADEON_PCIE_TX_GART_INVALIDATE_TLB	(1 << 8)
 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
 #define RADEON_PCIE_TX_GART_BASE	0x13
@@ -463,14 +463,9 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #define RADEON_PCIE_TX_GART_END_LO	0x16
 #define RADEON_PCIE_TX_GART_END_HI	0x17
 
-#define RADEON_IGPGART_INDEX            0x168
-#define RADEON_IGPGART_DATA             0x16c
-#define RADEON_IGPGART_UNK_18           0x18
-#define RADEON_IGPGART_CTRL             0x2b
-#define RADEON_IGPGART_BASE_ADDR        0x2c
-#define RADEON_IGPGART_FLUSH            0x2e
-#define RADEON_IGPGART_ENABLE           0x38
-#define RADEON_IGPGART_UNK_39           0x39
+#define RS400_NB_MC_INDEX               0x168
+#	define RS400_NB_MC_IND_WR_EN	(1 << 8)
+#define RS400_NB_MC_DATA                0x16c
 
 #define RS690_MC_INDEX                  0x78
 #   define RS690_MC_INDEX_MASK          0x1ff
@@ -478,33 +473,55 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #   define RS690_MC_INDEX_WR_ACK        0x7f
 #define RS690_MC_DATA                   0x7c
 
-#define RS690_MC_MISC_CNTL              0x18
-#define RS690_MC_GART_FEATURE_ID        0x2b
-#define RS690_MC_GART_BASE              0x2c
-#define RS690_MC_GART_CACHE_CNTL	0x2e
-#   define RS690_MC_GART_CC_NO_CHANGE   0x0
-#   define RS690_MC_GART_CC_CLEAR       0x1
-#   define RS690_MC_GART_CLEAR_STATUS   (1 << 1)
+/* MC indirect registers */
+#define RS400_MC_MISC_CNTL              0x18
+#	define RS400_DISABLE_GTW	(1 << 1)
+/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
+#	define RS400_GART_INDEX_REG_EN	(1 << 12)
+#	define RS690_BLOCK_GFX_D3_EN	(1 << 14)
+#define RS400_K8_FB_LOCATION            0x1e
+#define RS400_GART_FEATURE_ID           0x2b
+#	define RS400_HANG_EN	        (1 << 11)
+#	define RS400_TLB_ENABLE	        (1 << 18)
+#	define RS400_P2P_ENABLE	        (1 << 19)
+#	define RS400_GTW_LAC_EN	        (1 << 25)
+#	define RS400_2LEVEL_GART	(0 << 30)
+#	define RS400_1LEVEL_GART	(1 << 30)
+#	define RS400_PDC_EN	        (1 << 31)
+#define RS400_GART_BASE                 0x2c
+#define RS400_GART_CACHE_CNTRL          0x2e
+#	define RS400_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
+/* ??? */
+#       define RS690_MC_GART_CLEAR_STATUS   (1 << 1)
 #       define RS690_MC_GART_CLEAR_DONE     (0 << 1)
 #       define RS690_MC_GART_CLEAR_PENDING  (1 << 1)
-#define RS690_MC_AGP_SIZE               0x38
-#   define RS690_MC_GART_DIS            0x0
-#   define RS690_MC_GART_EN             0x1
-#   define RS690_MC_AGP_SIZE_32MB       (0 << 1)
-#   define RS690_MC_AGP_SIZE_64MB       (1 << 1)
-#   define RS690_MC_AGP_SIZE_128MB      (2 << 1)
-#   define RS690_MC_AGP_SIZE_256MB      (3 << 1)
-#   define RS690_MC_AGP_SIZE_512MB      (4 << 1)
-#   define RS690_MC_AGP_SIZE_1GB        (5 << 1)
-#   define RS690_MC_AGP_SIZE_2GB        (6 << 1)
-#define RS690_MC_AGP_MODE_CONTROL       0x39
+#define RS400_AGP_ADDRESS_SPACE_SIZE    0x38
+#	define RS400_GART_EN	        (1 << 0)
+#	define RS400_VA_SIZE_32MB	(0 << 1)
+#	define RS400_VA_SIZE_64MB	(1 << 1)
+#	define RS400_VA_SIZE_128MB	(2 << 1)
+#	define RS400_VA_SIZE_256MB	(3 << 1)
+#	define RS400_VA_SIZE_512MB	(4 << 1)
+#	define RS400_VA_SIZE_1GB	(5 << 1)
+#	define RS400_VA_SIZE_2GB	(6 << 1)
+#define RS400_AGP_MODE_CNTL             0x39
+#	define RS400_POST_GART_Q_SIZE	(1 << 18)
+#	define RS400_NONGART_SNOOP	(1 << 19)
+#	define RS400_AGP_RD_BUF_SIZE	(1 << 20)
+#	define RS400_REQ_TYPE_SNOOP_SHIFT 22
+#	define RS400_REQ_TYPE_SNOOP_MASK  0x3
+#	define RS400_REQ_TYPE_SNOOP_DIS	(1 << 24)
+#define RS400_MC_MISC_UMA_CNTL          0x5f
+#define RS400_MC_MCLK_CNTL              0x7a
+#define RS400_MC_UMA_DUALCH_CNTL        0x86
+
 #define RS690_MC_FB_LOCATION            0x100
 #define RS690_MC_AGP_LOCATION           0x101
 #define RS690_MC_AGP_BASE               0x102
 #define RS690_MC_AGP_BASE_2             0x103
 
 #define R520_MC_IND_INDEX 0x70
-#define R520_MC_IND_WR_EN (1<<24)
+#define R520_MC_IND_WR_EN (1 << 24)
 #define R520_MC_IND_DATA  0x74
 
 #define RV515_MC_FB_LOCATION 0x01
@@ -516,6 +533,8 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #define RADEON_MPP_TB_CONFIG		0x01c0
 #define RADEON_MEM_CNTL			0x0140
 #define RADEON_MEM_SDRAM_MODE_REG	0x0158
+#define RADEON_AGP_BASE_2		0x015c
+#define RS400_AGP_BASE_2		0x0164
 #define RADEON_AGP_BASE			0x0170
 
 #define RADEON_RB3D_COLOROFFSET		0x1c40
@@ -1128,10 +1147,10 @@ do {									\
 
 #define RADEON_WRITE_IGPGART( addr, val )				\
 do {									\
-	RADEON_WRITE( RADEON_IGPGART_INDEX,				\
-			((addr) & 0x7f) | (1 << 8));			\
-	RADEON_WRITE( RADEON_IGPGART_DATA, (val) );			\
-	RADEON_WRITE( RADEON_IGPGART_INDEX, 0x7f );			\
+	RADEON_WRITE( RS400_NB_MC_INDEX,				\
+			((addr) & 0x7f) | RS400_NB_MC_IND_WR_EN);	\
+	RADEON_WRITE( RS400_NB_MC_DATA, (val) );			\
+	RADEON_WRITE( RS400_NB_MC_INDEX, 0x7f );			\
 } while (0)
 
 #define RADEON_WRITE_PCIE( addr, val )					\