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authorAlan Hourihane <alanh@fairlite.demon.co.uk>2007-06-29 21:04:17 +0100
committerAlan Hourihane <alanh@fairlite.demon.co.uk>2007-06-29 21:04:17 +0100
commit70fd9351ed6c666def710fd61b542a7c975d9ac9 (patch)
treebceb4af8cfe2861436489bfa1081cfa7563ef501 /shared-core
parentadff58223f4568d084cf62d03d4ecfc3a6cec000 (diff)
Move out the code from i915_dma_cleanup to unload to match
existing code. This needs verifying.
Diffstat (limited to 'shared-core')
-rw-r--r--shared-core/i915_dma.c24
-rw-r--r--shared-core/i915_init.c10
2 files changed, 10 insertions, 24 deletions
diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c
index 008adc0a..7dd68954 100644
--- a/shared-core/i915_dma.c
+++ b/shared-core/i915_dma.c
@@ -91,30 +91,6 @@ int i915_dma_cleanup(drm_device_t * dev)
if (dev->irq)
drm_irq_uninstall(dev);
- if (dev->dev_private) {
- drm_i915_private_t *dev_priv =
- (drm_i915_private_t *) dev->dev_private;
-
- if (dev_priv->ring.virtual_start) {
- drm_core_ioremapfree(&dev_priv->ring.map, dev);
- }
-
- if (dev_priv->status_page_dmah) {
- drm_pci_free(dev, dev_priv->status_page_dmah);
- /* Need to rewrite hardware status page */
- I915_WRITE(I915REG_HWS_PGA, 0x1ffff000);
- }
- if (dev_priv->status_gfx_addr) {
- dev_priv->status_gfx_addr = 0;
- drm_core_ioremapfree(&dev_priv->hws_map, dev);
- I915_WRITE(I915REG_HWS_PGA, 0x1ffff000);
- }
- drm_free(dev->dev_private, sizeof(drm_i915_private_t),
- DRM_MEM_DRIVER);
-
- dev->dev_private = NULL;
- }
-
return 0;
}
diff --git a/shared-core/i915_init.c b/shared-core/i915_init.c
index e4a2cdef..fd102b35 100644
--- a/shared-core/i915_init.c
+++ b/shared-core/i915_init.c
@@ -257,6 +257,10 @@ int i915_driver_unload(drm_device_t *dev)
{
drm_i915_private_t *dev_priv = dev->dev_private;
+ if (dev_priv->ring.virtual_start) {
+ drm_core_ioremapfree(&dev_priv->ring.map, dev);
+ }
+
if (dev_priv->status_page_dmah) {
drm_pci_free(dev, dev_priv->status_page_dmah);
dev_priv->status_page_dmah = NULL;
@@ -266,6 +270,12 @@ int i915_driver_unload(drm_device_t *dev)
I915_WRITE(I915REG_HWS_PGA, 0x1ffff000);
}
+ if (dev_priv->status_gfx_addr) {
+ dev_priv->status_gfx_addr = 0;
+ drm_core_ioremapfree(&dev_priv->hws_map, dev);
+ I915_WRITE(I915REG_HWS_PGA, 0x1ffff000);
+ }
+
I915_WRITE(LP_RING + RING_LEN, 0);
intel_modeset_cleanup(dev);