diff options
| author | Eric Anholt <anholt@freebsd.org> | 2003-04-26 23:32:00 +0000 |
|---|---|---|
| committer | Eric Anholt <anholt@freebsd.org> | 2003-04-26 23:32:00 +0000 |
| commit | 766a1da2e5841959246abab9cf27c79d75636129 (patch) | |
| tree | 67b55933353dec843e44540882c61b87e81c8b88 /shared-core | |
| parent | a172ee2a18b715a6de9b8e914aecd8414a4f3b2d (diff) | |
Remove the map argument from DRM_*MEMORYBARRIER. Not all of the uses of
DRM_*MEMORYBARRIER we had were related to an MMIO space. This means
arch-specific code on the BSDs, unfortunately. Also add
DRM_MEMORYBARRIER() and change the DRM_READMEMORYBARRIER()s that used
to be read/write barriers to it.
Diffstat (limited to 'shared-core')
| -rw-r--r-- | shared-core/mga_drv.h | 8 | ||||
| -rw-r--r-- | shared-core/r128_drv.h | 2 | ||||
| -rw-r--r-- | shared-core/radeon_drv.h | 2 |
3 files changed, 6 insertions, 6 deletions
diff --git a/shared-core/mga_drv.h b/shared-core/mga_drv.h index 7efc89bc..feb389d6 100644 --- a/shared-core/mga_drv.h +++ b/shared-core/mga_drv.h @@ -131,7 +131,7 @@ extern int mga_getparam( DRM_IOCTL_ARGS ); extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv ); extern int mga_warp_init( drm_mga_private_t *dev_priv ); -#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER(dev_priv->primary) +#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER() #if defined(__linux__) && defined(__alpha__) #define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle)) @@ -142,12 +142,12 @@ extern int mga_warp_init( drm_mga_private_t *dev_priv ); #define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg))) #define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg))) -#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(dev_priv->mmio); MGA_DEREF( reg ) = val; } while (0) -#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(dev_priv->mmio); MGA_DEREF8( reg ) = val; } while (0) +#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0) +#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0) static inline u32 _MGA_READ(u32 *addr) { - DRM_READMEMORYBARRIER(dev_priv->mmio); + DRM_MEMORYBARRIER(); return *(volatile u32 *)addr; } #else diff --git a/shared-core/r128_drv.h b/shared-core/r128_drv.h index bd913878..3dee2e94 100644 --- a/shared-core/r128_drv.h +++ b/shared-core/r128_drv.h @@ -440,7 +440,7 @@ do { \ #if defined(__powerpc__) #define r128_flush_write_combine() (void) GET_RING_HEAD( &dev_priv->ring ) #else -#define r128_flush_write_combine() DRM_WRITEMEMORYBARRIER(dev_priv->ring_rptr) +#define r128_flush_write_combine() DRM_WRITEMEMORYBARRIER() #endif diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index ecf7cce0..07d747a6 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -852,7 +852,7 @@ do { \ #define COMMIT_RING() do { \ /* Flush writes to ring */ \ - DRM_READMEMORYBARRIER( dev_priv->mmio ); \ + DRM_MEMORYBARRIER(); \ GET_RING_HEAD( dev_priv ); \ RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ /* read from PCI bus to ensure correct posting */ \ |