diff options
| author | Alex Deucher <alex@botchco.com> | 2008-06-09 16:58:06 -0400 |
|---|---|---|
| committer | Alex Deucher <alex@botchco.com> | 2008-06-09 16:58:06 -0400 |
| commit | 4b8aecbde8e62af5370d5401d49a8ab8d089fe8e (patch) | |
| tree | fe37f5f59ce0649b4b163a3320c86e5c797e7945 /shared-core/radeon_cp.c | |
| parent | f6982b54c96bc871df94d01abad72a501e87aa65 (diff) | |
RADEON: Add untested support for RS400 chips
GART setup appears to work the same as RS480 chips.
Also RC4xx chips are actually RS400 based, not RS480 based.
Diffstat (limited to 'shared-core/radeon_cp.c')
| -rw-r--r-- | shared-core/radeon_cp.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index 696f12be..afe850c1 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -126,9 +126,10 @@ static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base) } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) { R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo); R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi); - } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480) { + } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); - RADEON_WRITE(RS480_AGP_BASE_2, 0); + RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi); } else { RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200) @@ -355,6 +356,7 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { DRM_INFO("Loading R300 Microcode\n"); for (i = 0; i < 256; i++) { |