diff options
author | Michel Dänzer <michel@tungstengraphics.com> | 2006-07-19 19:18:32 +0200 |
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committer | Michel Dänzer <michel@tungstengraphics.com> | 2006-07-19 19:18:32 +0200 |
commit | d5e0f8bdaf8769642950b8219f0e80f6b523817d (patch) | |
tree | 44c9326131dcca118f889452a13fd9c6f6024ff4 /shared-core/radeon_cp.c | |
parent | 2a47f6bfecea5dabcbf79d5e1aaf271f50070b89 (diff) |
Use RADEON_RB3D_DSTCACHE_CTLSTAT instead of RADEON_RB2D_DSTCACHE_CTLSTAT.
The latter seems to be a read-only mirror of the former.
Diffstat (limited to 'shared-core/radeon_cp.c')
-rw-r--r-- | shared-core/radeon_cp.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index 5f953a42..695b5ecb 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -864,13 +864,13 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; - tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT); - tmp |= RADEON_RB2D_DC_FLUSH_ALL; - RADEON_WRITE(RADEON_RB2D_DSTCACHE_CTLSTAT, tmp); + tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); + tmp |= RADEON_RB3D_DC_FLUSH_ALL; + RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); for (i = 0; i < dev_priv->usec_timeout; i++) { - if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT) - & RADEON_RB2D_DC_BUSY)) { + if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) + & RADEON_RB3D_DC_BUSY)) { return 0; } DRM_UDELAY(1); |