diff options
author | Ben Skeggs <skeggsb@gmail.com> | 2008-03-12 23:37:29 +1100 |
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committer | Ben Skeggs <skeggsb@gmail.com> | 2008-03-13 00:23:52 +1100 |
commit | 1766e1c07b03c6ccf545469663334be762c0bddf (patch) | |
tree | e60ee35ad5f843a882a1f4b65700ab66eea76c60 /shared-core/nv50_instmem.c | |
parent | 88bd1e4a350d011ec44f6786e0bfdf8fb386800c (diff) |
nv50: force channel vram access through vm
If we ever want to be able to use the 3D engine we have no choice. It
appears that the tiling setup (required for 3D on G8x) is in the page tables.
The immediate benefit of this change however is that it's now not possible
for a client to use the GPU to render over the top of important engine setup
tables, which also live in VRAM.
G8x VRAM size is limited to 512MiB at the moment, as we use a 1-1 mapping
of real vram pages to their offset within the start of a channel's VRAM
DMA object and only populate a single PDE for VRAM use.
Diffstat (limited to 'shared-core/nv50_instmem.c')
-rw-r--r-- | shared-core/nv50_instmem.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/shared-core/nv50_instmem.c b/shared-core/nv50_instmem.c index 9687ecbb..b7a51f09 100644 --- a/shared-core/nv50_instmem.c +++ b/shared-core/nv50_instmem.c @@ -243,7 +243,8 @@ nv50_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj, uin return -EINVAL; gpuobj->im_backing = nouveau_mem_alloc(dev, NV50_INSTMEM_PAGE_SIZE, - *sz, NOUVEAU_MEM_FB, + *sz, NOUVEAU_MEM_FB | + NOUVEAU_MEM_NOVM, (struct drm_file *)-2); if (!gpuobj->im_backing) { DRM_ERROR("Couldn't allocate vram to back PRAMIN pages\n"); |