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| author | Ben Skeggs <skeggsb@gmail.com> | 2007-07-15 17:18:15 +1000 |
|---|---|---|
| committer | Ben Skeggs <skeggsb@gmail.com> | 2007-07-17 13:51:14 +1000 |
| commit | ec67c2def9af16bf9252d6742aec815b817f135a (patch) | |
| tree | 90a1645b3fe9cd2b7c7ea36b79b609aaf2f2aa4c /shared-core/nv50_graph.c | |
| parent | 70a8a60a3e81c18f9c6485102cb226c340c3cd73 (diff) | |
nouveau: G8x PCIEGART
Actually a NV04-NV50 ttm backend for both PCI and PCIEGART, but PCIGART
support for G8X using the current mm has been hacked on top of it.
Diffstat (limited to 'shared-core/nv50_graph.c')
| -rw-r--r-- | shared-core/nv50_graph.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/shared-core/nv50_graph.c b/shared-core/nv50_graph.c index 54fe498b..6a04c158 100644 --- a/shared-core/nv50_graph.c +++ b/shared-core/nv50_graph.c @@ -271,7 +271,7 @@ nv50_graph_load_context(struct drm_device *dev, int channel) struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t inst = ((chan->ramin->instance >> 12) | (1<<31)); - int ret; + int ret; (void)ret; DRM_DEBUG("ch%d\n", channel); |