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authorAlan Hourihane <alanh@tungstengraphics.com>2008-02-18 22:35:46 +0000
committerAlan Hourihane <alanh@tungstengraphics.com>2008-02-18 22:35:46 +0000
commitf24ed2ad6c66e50268fd175146a1661ae4bbd350 (patch)
treedf804321f182607e8183df3375a16807ff42ba85 /shared-core/nv40_fb.c
parent2b1c9cd696049d23845870329d2b61a5873f7b13 (diff)
parent5d8c754bc2c720d70bbdeca6b294660105717a62 (diff)
Merge branch 'master' of git+ssh://git.freedesktop.org/git/mesa/drm into modesetting-101
Conflicts: linux-core/i915_fence.c linux-core/via_fence.c shared-core/i915_dma.c shared-core/i915_drv.h shared-core/i915_irq.c
Diffstat (limited to 'shared-core/nv40_fb.c')
-rw-r--r--shared-core/nv40_fb.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/shared-core/nv40_fb.c b/shared-core/nv40_fb.c
index ceae8079..ae784cb8 100644
--- a/shared-core/nv40_fb.c
+++ b/shared-core/nv40_fb.c
@@ -11,6 +11,13 @@ nv40_fb_init(struct drm_device *dev)
int num_tiles;
int i;
+ /* This is strictly a NV4x register (don't know about NV5x). */
+ /* The blob sets these to all kinds of values, and they mess up our setup. */
+ /* I got value 0x52802 instead. For some cards the blob even sets it back to 0x1. */
+ /* Note: the blob doesn't read this value, so i'm pretty sure this is safe for all cards. */
+ /* Any idea what this is? */
+ NV_WRITE(NV40_PFB_UNK_800, 0x1);
+
switch (dev_priv->chipset) {
case 0x40:
case 0x45: