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| author | Maarten Maathuis <madman2003@gmail.com> | 2008-02-02 12:46:31 +0100 |
|---|---|---|
| committer | Maarten Maathuis <madman2003@gmail.com> | 2008-02-02 12:46:47 +0100 |
| commit | 733e07663e50087ca1e9af8e9b5def556521e3b5 (patch) | |
| tree | 020554b852f868e5fb8d10a068d0547ff1582bf8 /shared-core/nv40_fb.c | |
| parent | c77b0937f290568604961fa0013691349c5fcf3b (diff) | |
nouveau: NV40 can/should now be able to run after the blob.
- Moved the fix from the ddx to drm, because it seemed more appropriate.
- Don't be shy, report if it works for you or not.
Diffstat (limited to 'shared-core/nv40_fb.c')
| -rw-r--r-- | shared-core/nv40_fb.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/shared-core/nv40_fb.c b/shared-core/nv40_fb.c index ceae8079..ae784cb8 100644 --- a/shared-core/nv40_fb.c +++ b/shared-core/nv40_fb.c @@ -11,6 +11,13 @@ nv40_fb_init(struct drm_device *dev) int num_tiles; int i; + /* This is strictly a NV4x register (don't know about NV5x). */ + /* The blob sets these to all kinds of values, and they mess up our setup. */ + /* I got value 0x52802 instead. For some cards the blob even sets it back to 0x1. */ + /* Note: the blob doesn't read this value, so i'm pretty sure this is safe for all cards. */ + /* Any idea what this is? */ + NV_WRITE(NV40_PFB_UNK_800, 0x1); + switch (dev_priv->chipset) { case 0x40: case 0x45: |